A low leakage 9t sram cell for ultra-low power operation. - Sheng Lin 006; Yong-Bin Kim; Fabrizio Lombardi (ACM Great Lakes Symposium on VLSI, 2008)

A Novel Hardened Design of a CMOS Memory Cell at 32nm. - Sheng Lin 006; Yong-Bin Kim; Fabrizio Lombardi (DFT, 2009)

Soft-Error Hardening Designs of Nanoscale CMOS Latches. - Sheng Lin 006; Yong-Bin Kim; Fabrizio Lombardi (VTS, 2009)

Read-out schemes for a CNTFET-based crossbar memory. - Sheng Lin 006; Yong-Bin Kim; Fabrizio Lombardi (ACM Great Lakes Symposium on VLSI, 2010)

Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability. - Sheng Lin 006; Yong-Bin Kim; Fabrizio Lombardi (Integr., 2010)

Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset. - Sheng Lin 006; Yong-Bin Kim; Fabrizio Lombardi (ICCD, 2011)

A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors. - Sheng Lin 006; Yong-Bin Kim; Fabrizio Lombardi (IEEE Trans. Very Large Scale Integr. Syst., 2011)