Sheng Liu

According to our database, Sheng Liu authored at least 32 papers between 2010 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

UNCER: A framework for uncertainty estimation and reduction in neural decoding of EEG signals.

Tiehang Duan, Zhenyi Wang, Sheng Liu, Yiyi Yin, Sargur N. Srihari

Neurocomputing, June, 2023

2022

Uncertainty Detection in EEG Neural Decoding Models.

Tiehang Duan, Zhenyi Wang, Sheng Liu, Sargur N. Srihari, Hui Yang

CoRR, 2022

MT-3000: a heterogeneous multi-zone processor for HPC.

Kai Lu, Yaohua Wang, Yang Guo, Chun Huang, Sheng Liu, Ruibo Wang, Jianbin Fang, Tao Tang, Zhaoyun Chen, Biwei Liu, Zhong Liu, Yuanwu Lei, Haiyan Sun

CCF Trans. High Perform. Comput., 2022

Adaptive Low-Cost Loop Expansion for Modulo Scheduling.

Hongli Zhong, Zhong Liu, Sheng Liu, Sheng Ma, Chen Li

Proceedings of the Network and Parallel Computing, 2022

Mentha: Enabling Sparse-Packing Computation on Systolic Arrays.

Minjin Tang, Mei Wen, Yasong Cao, Junzhong Shen, Jianchao Yang, Jiawei Fei, Yang Guo, Sheng Liu

Proceedings of the 51st International Conference on Parallel Processing, 2022

A dynamic computational memory address architecture for systolic array CNN accelerators.

Min Tang, Sheng Liu

Proceedings of the 24th IEEE Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, 2022

MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications.

Yasong Cao, Mei Wen, Junzhong Shen, Sheng Liu, Zhi Wang, Minjin Tang, Yahao Fang, Jianchao Yang, Renyu Yang, Yuhan Kang, Jiawei Fei

Proceedings of the 24th IEEE Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, 2022

2021

Advancing DSP into HPC, AI, and beyond: challenges, mechanisms, and future directions.

Yaohua Wang, Chen Li, Chang Liu, Sheng Liu, Yuanwu Lei, Jian Zhang, Yang Zhang, Yang Guo

CCF Trans. High Perform. Comput., 2021

Sparse Matrix-Vector Multiplication Cache Performance Evaluation and Design Exploration.

Jianfeng Cui, Kai Lu, Sheng Liu

Proceedings of the 29th International Symposium on Modeling, 2021

2018

A task-based multi-core allocation mechanism for packet acceleration.

Zerun Li, Yang Guo, Sheng Liu, Junyang Zhang

IEICE Electron. Express, 2018

Conflict-Free Block-with-Stride Access of 2D Storage Structure.

Rui Song, Guozhao Zeng, Sheng Liu, Haiyan Chen

Proceedings of the Algorithms and Architectures for Parallel Processing, 2018

2017

Round-trip DRAM Access Fairness in 3D NoC-based Many-core Systems.

Xiaowen Chen, Zhonghai Lu, Sheng Liu, Shuming Chen

ACM Trans. Embed. Comput. Syst., 2017

A Programmable Pre-emphasis Transmitter for SerDes in 40 nm CMOS.

Hongbing Tan, Haiyan Chen, Sheng Liu, Xikun Ma, Yaqing Chi

Proceedings of the Computer Engineering and Technology - 21st CCF Conference, 2017

Modeling and evaluation for gather/scatter operations in Vector-SIMD architectures.

Hongbing Tan, Haiyan Chen, Sheng Liu, Jianguo Wu

Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016

Dynamic Per-Warp Reconvergence Stack for Efficient Control Flow Handling in GPUs.

Yaohua Wang, Xiaowen Chen, Dong Wang, Sheng Liu

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs.

Sheng Liu, Haiyan Chen, Jianghua Wan, Yaohua Wang

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015

A New Memory Address Transformation for Continuous-Flow FFT Processors with SIMD Extension.

Chao Yang, Haiyan Chen, Sheng Liu, Sheng Ma

Proceedings of the Computer Engineering and Technology - 19th CCF Conference, 2015

2014

FT-Matrix: A Coordination-Aware Architecture for Signal Processing.

Shuming Chen, Yaohua Wang, Sheng Liu, Jianghua Wan, Haiyan Chen, Hengzhu Liu, Kai Zhang, Xiangyuan Liu, Xi Ning

IEEE Micro, 2014

2013

Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures.

Yaohua Wang, Shuming Chen, Hu Chen, Jianghua Wan, Kai Zhang, Sheng Liu

IEICE Trans. Inf. Syst., 2013

A novel QPP interleaver for parallel turbo decoder.

Wei Liu, Shuming Chen, Hu Chen, Yaohua Wang, Sheng Liu, Kai Zhang, Xi Ning

IEICE Electron. Express, 2013

2012

CMRF: a Configurable Matrix Register File for accelerating matrix operations on SIMD processors.

Kai Zhang, Shuming Chen, Hu Chen, Yaohua Wang, Xiaowen Chen, Sheng Liu, Wei Liu

IEICE Electron. Express, 2012

Erratum: Control-enhanced power-SIMD [IEICE Electronics Express Vol.9 (2012), No 14 pp 1147-1152].

Hui Yang, Shuming Chen, Tiebin Wu, Sheng Liu

IEICE Electron. Express, 2012

Control-enhanced power-SIMD.

Hui Yang, Shuming Chen, Tiebin Wu, Sheng Liu

IEICE Electron. Express, 2012

A cost conscious performance model for media processors.

Yaohua Wang, Shuming Chen, Kai Zhang, Jianghua Wan, Hu Chen, Sheng Liu, Xi Ning

IEICE Electron. Express, 2012

A novel parallel memory organization supporting multiple access types with matched memory modules.

Sheng Liu, Shuming Chen, Hu Chen, Yang Guo

IEICE Electron. Express, 2012

Architectural Implications for SIMD Processors in the Wireless Communication Domain.

Yaohua Wang, Kai Zhang, Jianghua Wan, Sheng Liu, Xi Ning, Shuming Chen

Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

2011

LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs.

Sheng Liu, Shuming Chen, Xi Ning, Jianghua Wan, Hu Chen, Kai Zhang, Yaohua Wang

IEICE Electron. Express, 2011

Matrix Odd-Even Partition: A High Power-Efficient Solution to the Small Grain Data Shuffle.

Sheng Liu, Shuming Chen, Jianghua Wan, Haiyan Chen, Yaohua Wang

Proceedings of the Sixth International Conference on Networking, Architecture, and Storage, 2011

Supporting Efficient Memory Conflicts Reduction Using the DMA Cache Technique in Vector DSPs.

Sheng Liu, Shuming Chen, Haiyan Chen, Shenggang Chen, Hu Chen

Proceedings of the Sixth International Conference on Networking, Architecture, and Storage, 2011

A Novel Highly Scalable Architecture with Partially Distributed Pipeline and Hardware/Software Instruction Encoding.

Hu Chen, Sheng Liu, Shuming Chen

Proceedings of the Sixth International Conference on Networking, Architecture, and Storage, 2011

Accelerating the data shuffle operations for FFT algorithms on SIMD DSPs.

Kai Zhang, Shuming Chen, Sheng Liu, Yaohua Wang, Junhui Huang

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform.

Shenggang Chen, Shuming Chen, Huitao Gu, Hu Chen, Yaming Yin, Xiaowen Chen, Shuwei Sun, Sheng Liu, Yaohua Wang

Proceedings of the 12th IEEE International Conference on High Performance Computing and Communications, 2010