Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform. - Shenggang Chen; Shuming Chen; Huitao Gu; Hu Chen; Yaming Yin; Xiaowen Chen; Shuwei Sun; Sheng Liu 001; Yaohua Wang (HPCC, 2010)

Accelerating the data shuffle operations for FFT algorithms on SIMD DSPs. - Kai Zhang 023; Shuming Chen; Sheng Liu 001; Yaohua Wang; Junhui Huang (ASICON, 2011)

A Novel Highly Scalable Architecture with Partially Distributed Pipeline and Hardware/Software Instruction Encoding. - Hu Chen; Sheng Liu 001; Shuming Chen (NAS, 2011)

Supporting Efficient Memory Conflicts Reduction Using the DMA Cache Technique in Vector DSPs. - Sheng Liu 001; Shuming Chen; Haiyan Chen; Shenggang Chen; Hu Chen (NAS, 2011)

Matrix Odd-Even Partition: A High Power-Efficient Solution to the Small Grain Data Shuffle. - Sheng Liu 001; Shuming Chen; Jianghua Wan; Haiyan Chen; Yaohua Wang (NAS, 2011)

LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs. - Sheng Liu 001; Shuming Chen; Xi Ning; Jianghua Wan; Hu Chen; Kai Zhang 023; Yaohua Wang (IEICE Electron. Express, 2011)

Architectural Implications for SIMD Processors in the Wireless Communication Domain. - Yaohua Wang; Kai Zhang 023; Jianghua Wan; Sheng Liu 001; Xi Ning; Shuming Chen (HPCC-ICESS, 2012)

A novel parallel memory organization supporting multiple access types with matched memory modules. - Sheng Liu 001; Shuming Chen; Hu Chen; Yang Guo 003 (IEICE Electron. Express, 2012)

A cost conscious performance model for media processors. - Yaohua Wang; Shuming Chen; Kai Zhang 023; Jianghua Wan; Hu Chen; Sheng Liu 001; Xi Ning (IEICE Electron. Express, 2012)

Control-enhanced power-SIMD. - Hui Yang; Shuming Chen; Tiebin Wu; Sheng Liu 001 (IEICE Electron. Express, 2012)

Erratum: Control-enhanced power-SIMD [IEICE Electronics Express Vol.9 (2012), No 14 pp 1147-1152]. - Hui Yang; Shuming Chen; Tiebin Wu; Sheng Liu 001 (IEICE Electron. Express, 2012)

CMRF: a Configurable Matrix Register File for accelerating matrix operations on SIMD processors. - Kai Zhang 023; Shuming Chen; Hu Chen; Yaohua Wang; Xiaowen Chen; Sheng Liu 001; Wei Liu 013 (IEICE Electron. Express, 2012)

A novel QPP interleaver for parallel turbo decoder. - Wei Liu 013; Shuming Chen; Hu Chen; Yaohua Wang; Sheng Liu 001; Kai Zhang 023; Xi Ning (IEICE Electron. Express, 2013)

Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures. - Yaohua Wang; Shuming Chen; Hu Chen; Jianghua Wan; Kai Zhang 023; Sheng Liu 001 (IEICE Trans. Inf. Syst., 2013)

FT-Matrix: A Coordination-Aware Architecture for Signal Processing. - Shuming Chen; Yaohua Wang; Sheng Liu 001; Jianghua Wan; Haiyan Chen; Hengzhu Liu; Kai Zhang 023; Xiangyuan Liu; Xi Ning (IEEE Micro, 2014)

A New Memory Address Transformation for Continuous-Flow FFT Processors with SIMD Extension. - Chao Yang 018; Haiyan Chen; Sheng Liu 001; Sheng Ma (NCCET, 2015)

Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs. - Sheng Liu 001; Haiyan Chen; Jianghua Wan; Yaohua Wang (ISVLSI, 2016)

Dynamic Per-Warp Reconvergence Stack for Efficient Control Flow Handling in GPUs. - Yaohua Wang; Xiaowen Chen; Dong Wang; Sheng Liu 001 (ISVLSI, 2016)

Modeling and evaluation for gather/scatter operations in Vector-SIMD architectures. - Hongbing Tan; Haiyan Chen; Sheng Liu 001; Jianguo Wu (ASAP, 2017)

A Programmable Pre-emphasis Transmitter for SerDes in 40 nm CMOS. - Hongbing Tan; Haiyan Chen; Sheng Liu 001; Xikun Ma; Yaqing Chi (NCCET, 2017)

Round-trip DRAM Access Fairness in 3D NoC-based Many-core Systems. - Xiaowen Chen; Zhonghai Lu; Sheng Liu 001; Shuming Chen (ACM Trans. Embed. Comput. Syst., 2017)

Conflict-Free Block-with-Stride Access of 2D Storage Structure. - Rui Song; Guozhao Zeng; Sheng Liu 001; Haiyan Chen (ICA3PP (3), 2018)

A task-based multi-core allocation mechanism for packet acceleration. - Zerun Li; Yang Guo 003; Sheng Liu 001; Junyang Zhang (IEICE Electron. Express, 2018)

Sparse Matrix-Vector Multiplication Cache Performance Evaluation and Design Exploration. - Jianfeng Cui; Kai Lu 001; Sheng Liu 001 (MASCOTS, 2021)

Advancing DSP into HPC, AI, and beyond: challenges, mechanisms, and future directions. - Yaohua Wang; Chen Li 015; Chang Liu 019; Sheng Liu 001; Yuanwu Lei; Jian Zhang 022; Yang Zhang; Yang Guo 003 (CCF Trans. High Perform. Comput., 2021)

MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications. - Yasong Cao; Mei Wen; Junzhong Shen; Sheng Liu 001; Zhi Wang; Minjin Tang; Yahao Fang; Jianchao Yang; Renyu Yang; Yuhan Kang; Jiawei Fei (HPCC/DSS/SmartCity/DependSys, 2022)

A dynamic computational memory address architecture for systolic array CNN accelerators. - Min Tang; Sheng Liu 001 (HPCC/DSS/SmartCity/DependSys, 2022)

Mentha: Enabling Sparse-Packing Computation on Systolic Arrays. - Minjin Tang; Mei Wen; Yasong Cao; Junzhong Shen; Jianchao Yang; Jiawei Fei; Yang Guo 003; Sheng Liu 001 (ICPP, 2022)

Adaptive Low-Cost Loop Expansion for Modulo Scheduling. - Hongli Zhong; Zhong Liu 003; Sheng Liu 001; Sheng Ma; Chen Li 015 (NPC, 2022)

MT-3000: a heterogeneous multi-zone processor for HPC. - Kai Lu 001; Yaohua Wang; Yang Guo 003; Chun Huang; Sheng Liu 001; Ruibo Wang; Jianbin Fang; Tao Tang 001; Zhaoyun Chen; Biwei Liu; Zhong Liu 003; Yuanwu Lei; et al. (CCF Trans. High Perform. Comput., 2022)

Uncertainty Detection in EEG Neural Decoding Models. - Tiehang Duan; Zhenyi Wang 001; Sheng Liu 001; Sargur N. Srihari; Hui Yang (CoRR, 2022)

UNCER: A framework for uncertainty estimation and reduction in neural decoding of EEG signals. - Tiehang Duan; Zhenyi Wang 001; Sheng Liu 001; Yiyi Yin; Sargur N. Srihari (Neurocomputing, 2023)

LWECC: A Lightweight ECC Technology for HPC Accelerators Supporting Multi-granularity Memory Access. - Lanting Guo; Haiyan Chen; Chen Li 015; Sheng Liu 001 (ISCAS, 2024)