A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur. - Tsung-Hsien Tsai; Ruey-Bin Sheen; Sheng-Yun Hsu; Ya-Tin Chang; Chih-Hsien Chang; Robert Bogdan Staszewski (ISSCC, 2022)