Double-Tree Scan: A Novel Low-Power Scan-Path Architecture. - Bhargab B. Bhattacharya; Sharad C. Seth; Sheng Zhang 008 (ITC, 2003)

Low-Energy BIST Design for Scan-based Logic Circuits. - Bhargab B. Bhattacharya; Sharad C. Seth; Sheng Zhang 008 (VLSI Design, 2003)

Efficient Test Compaction for Pseudo-Random Testing. - Sheng Zhang 008; Sharad C. Seth; Bhargab B. Bhattacharya (Asian Test Symposium, 2005)

On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design. - Sheng Zhang 008; Sharad C. Seth; Bhargab B. Bhattacharya (VLSI Design, 2005)

Planar Straight-Line Embedding of Double-Tree Scan Architecture on a Rectangular Grid. - Indranil Saha; Bhargab B. Bhattacharya; Sheng Zhang 008; Sharad C. Seth (Fundam. Informaticae, 2008)