Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform. - Shenggang Chen; Shuming Chen; Huitao Gu; Hu Chen; Yaming Yin; Xiaowen Chen; Shuwei Sun; Sheng Liu 001; Yaohua Wang (HPCC, 2010)

Performance impact of SMP-cluster on the On-chip Large-scale Parallel Computing architecture. - Shenggang Chen; Shuming Chen; Yaming Yin (IPDPS Workshops, 2010)

Multiple Search Centers Based Fast Motion Estimation Algorithm for H.264/AVC. - Huitao Gu; Shuming Chen; Shuwei Sun; Shenggang Chen; Xiaowen Chen (PDCAT, 2010)

P3-CABAC: A Nonstandard Tri-Thread Parallel Evolution of CABAC in the Manycore Era. - Shenggang Chen; Shuming Chen; Shuwei Sun (IEEE Trans. Circuits Syst. Video Technol., 2010)

Design and chip implementation of a heterogeneous multi-core DSP. - Shuming Chen; Xiaowen Chen; Yi Xu; Jianghua Wan; Jianzhuang Lu; Xiangyuan Liu; Shenggang Chen (ASP-DAC, 2011)

AIFSP: An Adaptive Instruction Flow Stream Processor. - Yaohua Wang; Shuming Chen; Jianghua Wan; Kai Zhang 023; Shenggang Chen (ISVLSI, 2011)

Supporting Efficient Memory Conflicts Reduction Using the DMA Cache Technique in Vector DSPs. - Sheng Liu 001; Shuming Chen; Haiyan Chen; Shenggang Chen; Hu Chen (NAS, 2011)

Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property. - Xiaowen Chen; Zhonghai Lu; Axel Jantsch; Shuming Chen; Shenggang Chen; Huitao Gu (Comput. Electr. Eng., 2013)

Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs. - Xiaowen Chen; Zhonghai Lu; Yang Li; Axel Jantsch; Xueqian Zhao; Shuming Chen; Yang Guo 003; Zonglin Liu; Jianzhuang Lu; Jianghua Wan; Shuwei Sun; Shenggang Chen; et al. (ISVLSI, 2015)

Express Ring: a multi-layer and non-blocking NoC architecture. - Chen Li 015; Sheng Ma; Shenggang Chen; Yang Guo 003; Peng Wang 036 (IEICE Electron. Express, 2015)

Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications. - Xiaowen Chen; Zhonghai Lu; Axel Jantsch; Shuming Chen; Yang Guo 003; Shenggang Chen; Hu Chen (J. Electr. Comput. Eng., 2015)

Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips. - Xiaowen Chen; Zhonghai Lu; Axel Jantsch; Shuming Chen; Yang Guo 003; Shenggang Chen; Hu Chen; Man Liao (J. Softw., 2015)

Multi-bit transient fault control for NoC links using 2D fault coding method. - Xiaowen Chen; Zhonghai Lu; Yuanwu Lei; Yaohua Wang; Shenggang Chen (NOCS, 2016)

Iteration Interleaving-Based SIMD Lane Partition. - Yaohua Wang; Dong Wang; Shuming Chen; Zonglin Liu; Shenggang Chen; Xiaowen Chen; Xu Zhou (ACM Trans. Archit. Code Optim., 2016)

ANN Based Admission Control for On-Chip Networks. - Boqian Wang; Zhonghai Lu; Shenggang Chen (DAC, 2019)

Improving the DRAM Access Efficiency for Matrix Multiplication on Multicore Accelerators. - Sheng Ma; Yang Guo 003; Shenggang Chen; Libo Huang; Zhiying Wang 003 (DATE, 2019)

Hardware Acceleration of Multilayer Perceptron Based on Inter-Layer Optimization. - Shenggang Chen; Zhonghai Lu (ICCD, 2019)

Coordinated DMA: Improving the DRAM Access Efficiency for Matrix Multiplication. - Sheng Ma; Zhong Liu 003; Shenggang Chen; Libo Huang; Yang Guo 003; Zhiying Wang 003; Meidi Zhang (IEEE Trans. Parallel Distributed Syst., 2019)