Optimizing Mixer Noise Performance: A 2.4 GHz Gilbert Downconversion Mixer for W-CDMA Application. - Shenggao Li; Yue Wu; Chunlei Shi; Mohammed Ismail 001 (VLSI, 1999)

A Lower Power CMOS Micromixer for GHz Wireless Applications. - Yue Wu; Shenggao Li; Mohammed Ismail 001; Håkan K. Olsson (VLSI, 1999)

The Implementation of a VHDL-AMS to SPICE Converter. - Shenggao Li; Brian Okoon; Mona Mostafa Hella; Mohammed Ismail 001; Maya Rubeiz (J. VLSI Signal Process., 1999)

A 10-GHz CMOS quadrature LC-VCO for multirate optical applications. - Shenggao Li; Issy Kipnis; Mohammed Ismail 001 (IEEE J. Solid State Circuits, 2003)

Clock generation for a 32nm server processor with scalable cores. - Shenggao Li; Ashwin Krishnakumar; Edward Helder; Roan Nicholson; Vivian Jia (ISSCC, 2011)

5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family. - Stefan Rusu; Harry Muljono; David Ayers; Simon M. Tam; Wei Chen 129; Aaron Martin; Shenggao Li; Sujal Vora; Raj Varada; Eddie Wang (ISSCC, 2014)

A 22 nm 15-Core Enterprise Xeon® Processor Family. - Stefan Rusu; Harry Muljono; David Ayers; Simon M. Tam; Wei Chen 129; Aaron Martin; Shenggao Li; Sujal Vora; Raj Varada; Eddie Wang (IEEE J. Solid State Circuits, 2015)

A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS. - Shenggao Li; Fulvio Spagna; Ji Chen; Xiaoqing Wang; Luke Tong; Sujatha Gowder; Wenyan Jia; Roan Nicholson; Sitaraman Iyer; Rui Song; Lily Li; Meng-hung Chen; et al. (A-SSCC, 2018)

Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling. - Shenggao Li; Chien-Chun Tsai; Eric Soenen; Frank J. C. Lee; Cheng-Hsiang Hsieh (A-SSCC, 2021)

Quadruped Robot Hopping on Two Legs. - Shenggao Li; Hua Chen 007; Wei Zhang 013; Patrick M. Wensing (IROS, 2021)

Interconnect in the Era of 3DIC. - Shenggao Li; Mu-Shan Lin; Wei-Chih Chen; Chien-Chun Tsai (CICC, 2022)

A Geometric Sufficient Condition for Contact Wrench Feasibility. - Shenggao Li; Hua Chen 007; Wei Zhang 013; Patrick M. Wensing (IEEE Robotics Autom. Lett., 2022)

Current Mirrors with Tapered Stacked-Gates for Area Saving or Noise Improvement in 3nm FinFET Process. - Chu-En Hsia; Chin-Ho Chang; Yung-Shun Chen; Po-Yu Lai; Ching Lin Jen; Yung-Chow Peng; Shenggao Li (VLSI Technology and Circuits, 2024)

A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Tze-Chiang Huang; Wen-Hung Huang; Kate Huang; Yu-Chi Chen; Alex Liu; Yu-Jie Huang; Jimmy Wang; Shu-Chun Yang; Nai-Chen Cheng 001; et al. (VLSI Technology and Circuits, 2024)

Simultaneous Locomotion Mode Classification and Continuous Gait Phase Estimation for Transtibial Prostheses. - Ryan R. Posh; Shenggao Li; Patrick M. Wensing (CoRR, 2024)

UCle-Compliant Chiplet Interconnect Design Leveraging Cutting-Edge Packaging Technologies. - Yu-Jie Huang; Mu-Shan Lin; Chien-Chun Tsai; Wei-Chih Chen; Hsin-Hung Kuo; Shu-Chun Yang; Shenggao Li (CICC, 2025)

36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Wei-Chih Chen; Wen-Hung Huang; Yu-Chi Chen; Yu-Jie Huang; Alan J. Drake; Chin-Hua Wen; Paul Ranucci; Hsin-Hung Kuo; Aidong Yin; et al. (ISSCC, 2025)

TSMC in the Silicon Photonics Era - an Electrical Perspective. - Mikael Sahrling; Shenggao Li; Frank Lee 004; Stefan Rusu (OFC, 2025)