Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. - Xianlong Hong; Gang Huang; Yici Cai; Jiangchun Gu; Sheqin Dong; Chung-Kuan Cheng; Jun Gu (ICCAD, 2000)

VLSI block placement using less flexibility first principles. - Sheqin Dong; Xianlong Hong; Youliang Wu; Yizhou Lin; Jun Gu (ASP-DAC, 2001)

VLSI floorplanning with boundary constraints based on corner block list. - Yuchun Ma; Sheqin Dong; Xianlong Hong; Yici Cai; Chung-Kuan Cheng; Jun Gu (ASP-DAC, 2001)

Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Yici Cai; Chung-Kuan Cheng; Jun Gu (DAC, 2001)

ECBL: an extended corner block list with solution space including optimum placement. - Shuo Zhou; Sheqin Dong; Chung-Kuan Cheng; Jun Gu (ISPD, 2001)

Floorplanning with abutment constraints based on corner block list. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Yici Cai; Chung-Kuan Cheng; Jun Gu (Integr., 2001)

An Optimum Placement Search Algorithm Based on Extended Corner Block List. - Sheqin Dong; Shuo Zhou; Xianlong Hong; Chung-Kuan Cheng; Jun Gu; Yici Cai (J. Comput. Sci. Technol., 2002)

A buffer planning algorithm based on dead space redistribution. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Yici Cai; Chung-Kuan Cheng; Jun Gu (ASP-DAC, 2003)

VLSI module placement with pre-placed modules and considering congestion using solution space smoothing. - Sheqin Dong; Xianlong Hong; Xin Qi; Ruijie Wang 006; Song Chen 001; Jun Gu (ASP-DAC, 2003)

Dynamic global buffer planning optimization based on detail block locating and congestion analysis. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Yici Cai; Chung-Kuan Cheng; Jun Gu (DAC, 2003)

Evaluating a bounded slice-line grid assignment in O(nlogn) time. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Yici Cai; Chung-Kuan Cheng; Jun Gu (ISCAS (4), 2003)

Algorithms for analog VLSI 2D stack generation and block merging. - Rui Liu; Sheqin Dong; Xianlong Hong; Di Long; Jun Gu (ISCAS (4), 2003)

Arbitrary convex and concave rectilinear block packing based on corner block list. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Yici Cai; Song Chen 001; Chung-Kuan Cheng; Jun Gu (ISCAS (5), 2003)

An integrated floorplanning with an efficient buffer planning algorithm. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Yici Cai; Chung-Kuan Cheng; Jun Gu (ISPD, 2003)

VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing. - Sheqin Dong; Xianlong Hong; Song Chen 001; Xin Qi; Ruijie Wang 006; Jun Gu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle. - Sheqin Dong; Xianlong Hong; Yuliang Wu; Jun Gu (J. Comput. Sci. Technol., 2003)

A buffer planning algorithm with congestion optimization. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Yici Cai; Chung-Kuan Cheng; Jun Gu (ASP-DAC, 2004)

Buffer allocation algorithm with consideration of routing congestion. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Yici Cai; Chung-Kuan Cheng; Jun Gu (ASP-DAC, 2004)

Module placement based on quadratic programming and rectangle packing using less flexibility first principle. - Sheqin Dong; Zhong Yang; Xianlong Hong; Yuliang Wu (ISCAS (5), 2004)

A buffer planning algorithm for chip-level floorplanning. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Yici Cai; Chung-Kuan Cheng; Jun Gu (Sci. China Ser. F Inf. Sci., 2004)

Corner block list representation and its application with boundary constraints. - Xianlong Hong; Yuchun Ma; Sheqin Dong; Yici Cai; Chung-Kuan Cheng; Jun Gu (Sci. China Ser. F Inf. Sci., 2004)

Fast Evaluation of Bounded Slice-Line Grid. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Chung-Kuan Cheng; Jun Gu (J. Comput. Sci. Technol., 2004)

Corner block list representation and its application to floorplan optimization. - Xianlong Hong; Sheqin Dong; Gang Huang; Yici Cai; Chung-Kuan Cheng; Jun Gu (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

Stairway compaction using corner block list and its applications with rectilinear blocks. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Yici Cai; Chung-Kuan Cheng; Jun Gu (ACM Trans. Design Autom. Electr. Syst., 2004)

An improved P-admissible floorplan representation based on Corner Block List. - Renshen Wang; Sheqin Dong; Xianlong Hong (ASP-DAC, 2005)

LFF algorithm for heterogeneous FPGA floorplanning. - Jun Yuan; Sheqin Dong; Xianlong Hong; Yuliang Wu (ASP-DAC, 2005)

An efficient algorithm to fixed-outline floorplanning based on instance augmentation. - Rong Liu; Sheqin Dong; Xianlong Hong (CAD/Graphics, 2005)

A New Buffer Planning Algorithm Based on Room Resizing. - Hongjie Bai; Sheqin Dong; Xianlong Hong; Song Chen 001 (EUC, 2005)

Fixed-outline floorplanning based on common subsequence. - Rong Liu; Sheqin Dong; Xianlong Hong (ACM Great Lakes Symposium on VLSI, 2005)

VLSI block placement with alignment constraints based on corner block list. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Chung-Kuan Cheng (ISCAS (6), 2005)

Fixed-outline floorplanning with constraints through instance augmentation. - Rong Liu; Sheqin Dong; Xianlong Hong; Yoji Kajitani (ISCAS (2), 2005)

Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit. - Di Long; Xianlong Hong; Sheqin Dong (ISCAS (3), 2005)

Performance constrained floorplanning based on partial clustering [IC layout]. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Chung-Kuan Cheng (ISCAS (2), 2005)

A new approach based on LFF for optimization of dynamic hardware reconfigurations. - Zhe Zhou; Sheqin Dong; Xianlong Hong; Yuliang Wu; Yoji Kajitani (ISCAS (2), 2005)

Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Chung-Kuan Cheng (ISQED, 2005)

Buffer Planning Algorithm Based on Partial Clustered Floorplanning. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Chung-Kuan Cheng (ISQED, 2005)

Buffer planning as an Integral part of floorplanning with consideration of routing congestion. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Chung-Kuan Cheng; Jun Gu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. - Liu Yang; Sheqin Dong; Xianlong Hong; Yuchun Ma (APCCAS, 2006)

Signal-path driven partition and placement for analog circuit. - Di Long; Xianlong Hong; Sheqin Dong (ASP-DAC, 2006)

Buffer planning based on block exchanging. - Hongjie Bai; Sheqin Dong; Xianlong Hong; Song Chen 001 (ISCAS, 2006)

Floorplanning for 2.5-D system integration using multi-layer-BSG structure. - Sheqin Dong; Shuyi Zheng; Xianlong Hong (ISCAS, 2006)

On handling the fixed-outline constraints of floorplanning using less flexibility first principles. - Shaojun Wei; Sheqin Dong; Xianlong Hong; Youliang Wu (ISCAS, 2006)

A Novel Tour Construction Heuristic for Traveling Salesman Problem Using LFF Principle. - Sheqin Dong; Fan Guo; Jun Yuan; Rensheng Wang; Xianlong Hong (JCIS, 2006)

Stochastic Local Search Using the Search Space Smoothing Meta-Heuristic: A Case Study. - Sheqin Dong; Fan Guo; Jun Yuan; Rensheng Wang; Xianlong Hong (JCIS, 2006)

Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree. - Sheqin Dong; Rensheng Wang; Fan Guo; Jun Yuan; Xianlong Hong (JCIS, 2006)

A Heterogeneous Dependency Graph as Intermediate Representation for Instruction Set Customization. - Kang Zhao; Jinian Bian; Sheqin Dong (JCIS, 2006)

General Floorplans with L/T-Shaped Blocks Using Corner Block List. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Chung-Kuan Cheng; Jun Gu (J. Comput. Sci. Technol., 2006)

VLSI Block Placement With Alignment Constraints. - Song Chen 001; Sheqin Dong; Xianlong Hong; Yuchun Ma; Chung-Kuan Cheng (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. - Jiayi Liu; Sheqin Dong; Yuchun Ma; Di Long; Xianlong Hong (ASP-DAC, 2007)

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. - Yuchun Ma; Zhuoyuan Li 003; Jason Cong; Xianlong Hong; Glenn Reinman; Sheqin Dong; Qiang Zhou 001 (ASP-DAC, 2007)

A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. - Kang Zhao; Jinian Bian; Sheqin Dong (CSCWD, 2007)

An effective buffer planning algorithm for IP based fixed-outline SOC placement. - Ou He; Sheqin Dong; Jinian Bian; Yuchun Ma; Xianlong Hong (ACM Great Lakes Symposium on VLSI, 2007)

A Fast 3D-BSG Algorithm for 3D Packing Problem. - Lingyi Zhang; Sheqin Dong; Xianlong Hong; Yuchun Ma (ISCAS, 2007)

Congestion Driven Buffer Planning for X-Architecture. - Hongjie Bai; Sheqin Dong; Xianlong Hong (ISQED, 2007)

Interconnect Power Optimization Based on Timing Analysis. - Liu Yang; Sheqin Dong; Yuchun Ma; Xianlong Hong (ISVLSI, 2007)

An accurate and efficient probabilistic congestion estimation model in x architecture. - Yaoguang Wei; Sheqin Dong; Xianlong Hong; Yuchun Ma (SLIP, 2007)

APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement. - Yaoguang Wei; Sheqin Dong; Xianlong Hong (Integr., 2007)

LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. - Xin Li; Yuchun Ma; Xianlong Hong; Sheqin Dong; Jason Cong (ASP-DAC, 2008)

Symmetry constraint based on mismatch analysis for analog layout in SOI technology. - Jiayi Liu; Sheqin Dong; Xianlong Hong; Yibo Wang 009; Ou He; Satoshi Goto (ASP-DAC, 2008)

Cache miss reduction through hardware-assisted loop optimization. - Kang Zhao; Jinian Bian; Chenqian Jiang; Sheqin Dong; Satoshi Goto (CSCWD, 2008)

HyMacs: hybrid memory access optimization based on custom-instruction scheduling. - Kang Zhao; Jinian Bian; Sheqin Dong; Yang Song 002; Satoshi Goto (ACM Great Lakes Symposium on VLSI, 2008)

A novel fixed-outline floorplanner with zero deadspace for hierarchical design. - Ou He; Sheqin Dong; Jinian Bian; Satoshi Goto; Chung-Kuan Cheng (ICCAD, 2008)

Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration. - Kang Zhao; Jinian Bian; Sheqin Dong; Yang Song 002; Satoshi Goto (ISQED, 2008)

Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design. - Kang Zhao; Jinian Bian; Sheqin Dong; Yang Song 002; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System. - Kang Zhao; Jinian Bian; Sheqin Dong; Yang Song 002; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Voltage-island driven floorplanning considering level-shifter positions. - Bei Yu 001; Sheqin Dong; Satoshi Goto; Song Chen 001 (ACM Great Lakes Symposium on VLSI, 2009)

Buffer Planning for 3D ICs. - Sheqin Dong; Hongjie Bai; Xianlong Hong; Satoshi Goto (ISCAS, 2009)

Simultaneous buffer and interlayer via planning for 3D floorplanning. - Xu He; Sheqin Dong; Yuchun Ma; Xianlong Hong (ISQED, 2009)

Integrated interlayer via planning and pin assignment for 3D ICs. - Xu He; Sheqin Dong; Xianlong Hong; Satoshi Goto (SLIP, 2009)

Voltage and Level-Shifter Assignment Driven Floorplanning. - Bei Yu 001; Sheqin Dong; Song Chen 001; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis. - Kang Zhao; Jinian Bian; Sheqin Dong; Yang Song 002; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Floorplanning and topology generation for application-specific network-on-chip. - Bei Yu 001; Sheqin Dong; Song Chen 001; Satoshi Goto (ASP-DAC, 2010)

Bus via reduction based on floorplan revising. - Ou He; Sheqin Dong; Jinian Bian; Satoshi Goto; Chung-Kuan Cheng (ACM Great Lakes Symposium on VLSI, 2010)

A revisit to voltage partitioning problem. - Tao Lin; Sheqin Dong; Bei Yu 001; Song Chen 001; Satoshi Goto (ACM Great Lakes Symposium on VLSI, 2010)

Wirelength-driven force-directed 3D FPGA placement. - Wentao Sui; Sheqin Dong; Jinian Bian (ACM Great Lakes Symposium on VLSI, 2010)

Fixed outline multi-bend bus driven floorplanning. - Wenxu Sheng; Sheqin Dong; Yuliang Wu; Satoshi Goto (ISQED, 2010)

Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs. - Xu He; Sheqin Dong; Yuchun Ma (Integr., 2010)

Through-Silicon-Via assignment for 3D ICs. - Jianchang Ao; Sheqin Dong; Song Chen 001; Satoshi Goto (ASICON, 2011)

Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. - Kan Wang; Yuchun Ma; Sheqin Dong; Yu Wang 002; Xianlong Hong; Jason Cong (ASP-DAC, 2011)

Network flow-based simultaneous retiming and slack budgeting for low power design. - Bei Yu 001; Sheqin Dong; Yuchun Ma; Tao Lin; Yu Wang 002; Song Chen 001; Satoshi Goto (ASP-DAC, 2011)

Novel and efficient min cut based voltage assignment in gate level. - Tao Lin; Sheqin Dong; Song Chen 001; Yuchun Ma; Ou He; Satoshi Goto (ISQED, 2011)

Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion. - Wei Zhong; Bei Yu 001; Song Chen 001; Takeshi Yoshimura; Sheqin Dong; Satoshi Goto (ISQED, 2011)

Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. - Kan Wang; Sheqin Dong; Yuchun Ma; Yu Wang 002; Xianlong Hong; Jason Cong (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Buffer Planning for IP Placement Using Sliced-LFF. - Ou He; Sheqin Dong; Jinian Bian; Satoshi Goto (VLSI Design, 2011)

Linear optimal one-sided single-detour algorithm for untangling twisted bus. - Tao Lin; Sheqin Dong; Song Chen 001; Satoshi Goto (ASP-DAC, 2012)

Voltage island-driven power optimization for application specific network-on-chip design. - Kan Wang; Sheqin Dong; Satoshi Goto (ACM Great Lakes Symposium on VLSI, 2012)

Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. - Kan Wang; Sheqin Dong; Yuchun Ma; Satoshi Goto; Jason Cong (ISQED, 2012)

Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System. - Haiqi Wang; Sheqin Dong; Tao Lin; Song Chen 001; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips. - Wei Zhong; Takeshi Yoshimura; Bei Yu 001; Song Chen 001; Sheqin Dong; Satoshi Goto (IEICE Trans. Electron., 2012)

UNISM: Unified Scheduling and Mapping for General Networks on Chip. - Ou He; Sheqin Dong; Wooyoung Jang; Jinian Bian; David Z. Pan (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Power optimization for application-specific 3D network-on-chip with multiple supply voltages. - Kan Wang; Sheqin Dong (ASP-DAC, 2013)

Delay-driven layer assignment in global routing under multi-tier interconnect structure. - Jianchang Ao; Sheqin Dong; Song Chen 001; Satoshi Goto (ISPD, 2013)

Escape routing of mixed-pattern signals based on staggered-pin-array PCBs. - Kan Wang; Huaxi Wang; Sheqin Dong (ISPD, 2013)

Multi-bend bus-driven floorplanning considering fixed-outline constraints. - Wenxu Sheng; Sheqin Dong (Integr., 2013)

Post-floorplanning power optimization for MSV-driven application specific NoC design. - Kan Wang; Sheqin Dong (ISCAS, 2014)

Multi-Voltage and Level-Shifter Assignment Driven Floorplanning. - Bei Yu 001; Sheqin Dong; Satoshi Goto (CoRR, 2014)

Mixed-Crossing-Avoided Escape Routing of Mixed-Pattern Signals on Staggered-Pin-Array PCBs. - Kan Wang; Sheqin Dong; Huaxi Wang; Qian Chen; Tao Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Delay-Driven and Antenna-Aware Layer Assignment in Global Routing Under Multitier Interconnect Structure. - Sheqin Dong; Jianchang Ao; Fuqi Luo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Ordered Escape routing for grid pin array based on Min-cost Multi-commodity Flow. - Fengxian Jiao; Sheqin Dong (ASP-DAC, 2016)

TSF3D: MSV-Driven Power Optimization for Application-Specific 3D Network-on-Chip. - Kan Wang; Sheqin Dong; Fengxian Jiao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips. - Fengxian Jiao; Sheqin Dong; Bei Yu 001; Bing Li 005; Ulf Schlichtmann (ISCAS, 2018)

A Novel Mixed-Size Fixed-Outline Floorplacement Algorithm. - Qian Chen; Sheqin Dong (ISVLSI, 2018)

Ordered Escape Routing with Consideration of Differential Pair and Blockage. - Fengxian Jiao; Sheqin Dong (ACM Trans. Design Autom. Electr. Syst., 2018)

A Constraint-Driven Compact Model with Partition Strategy for Ordered Escape Routing. - Zhaopo Liao; Sheqin Dong (ACM Great Lakes Symposium on VLSI, 2020)

MC-MCF: A Multi-Capacity Model for Ordered Escape Routing. - Zhenyi Gao; Sheqin Dong; Zhicong Tang; Wenjian Yu (ISQED, 2023)

MORE-Router+: Multilayer Multi-capacity ORdered Escape Routing via Bus-oriented Layer Assignment. - Zhenyi Gao; Sheqin Dong; Zifei Cheng; Wenjian Yu (ISQED, 2024)

MCMCF-Router: Multi-capacity Ordered Escape Routing Algorithms for Grid/Staggered Pin Array. - Zhenyi Gao; Sheqin Dong; Zhicong Tang; Wenjian Yu (ACM Trans. Design Autom. Electr. Syst., 2024)