M-CHECK: a multiple engine combinational equivalence checker. - Sherief Reda; Ayman Wahba; Ashraf Salem (ISCAS, 2000)

Combinational equivalence checking using Boolean satisfiability and binary decision diagrams. - Sherief Reda; Ashraf Salem (DATE, 2001)

On the use of don't cares during symbolic reachability analysis. - Sherief Reda; Ayman Wahba; Ashraf Salem; Dominique Borrione; M. Ghonaimy (ISCAS (5), 2001)

Reducing Test Application Time Through Test Data Mutation Encoding. - Sherief Reda; Alex Orailoglu (DATE, 2002)

On the Relation between SAT and BDDs for Equivalence Checking. - Sherief Reda; Rolf Drechsler; Alex Orailoglu (ISQED, 2002)

Border Length Minimization in DNA Array Design. - Andrew B. Kahng; Ion I. Mandoiu; Pavel A. Pevzner; Sherief Reda; Alexander Zelikovsky (WABI, 2002)

Evaluation of Placement Techniques for DNA Probe Array Layout. - Andrew B. Kahng; Ion I. Mandoiu; Sherief Reda; Xu Xu 001; Alexander Zelikovsky (ICCAD, 2003)

Design Flow Enhancements for DNA Arrays. - Andrew B. Kahng; Ion I. Mandoiu; Sherief Reda; Xu Xu 001; Alexander Zelikovsky (ICCD, 2003)

Engineering a scalable placement heuristic for DNA probe arrays. - Andrew B. Kahng; Ion I. Mandoiu; Pavel A. Pevzner; Sherief Reda; Alexander Zelikovsky (RECOMB, 2003)

Combinatorial group testing methods for the BIST diagnosis problem. - Andrew B. Kahng; Sherief Reda (ASP-DAC, 2004)

Placement feedback: a concept and method for better min-cut placements. - Andrew B. Kahng; Sherief Reda (DAC, 2004)

Boosting: Min-Cut Placement with Improved Signal Delay. - Andrew B. Kahng; Igor L. Markov; Sherief Reda (DATE, 2004)

On legalization of row-based placements. - Andrew B. Kahng; Igor L. Markov; Sherief Reda (ACM Great Lakes Symposium on VLSI, 2004)

Scalable Heuristics for Design of DNA Probe Arrays. - Andrew B. Kahng; Ion I. Mandoiu; Pavel A. Pevzner; Sherief Reda; Alexander Zelikovsky (J. Comput. Biol., 2004)

Match twice and stitch: a new TSP tour construction heuristic. - Andrew B. Kahng; Sherief Reda (Oper. Res. Lett., 2004)

Power-aware placement. - Yongseok Cheon; Pei-Hsin Ho; Andrew B. Kahng; Sherief Reda; Qinke Wang (DAC, 2005)

Intrinsic shortest path length: a new, accurate a priori wirelength estimator. - Andrew B. Kahng; Sherief Reda (ICCAD, 2005)

Architecture and details of a high quality, large-scale analytical placer. - Andrew B. Kahng; Sherief Reda; Qinke Wang (ICCAD, 2005)

A semi-persistent clustering technique for VLSI circuit placement. - Charles J. Alpert; Andrew B. Kahng; Gi-Joon Nam; Sherief Reda; Paul Villarrubia (ISPD, 2005)

Evaluation of placer suboptimality via zero-change netlist transformations. - Andrew B. Kahng; Sherief Reda (ISPD, 2005)

APlace: a general analytic placement framework. - Andrew B. Kahng; Sherief Reda; Qinke Wang (ISPD, 2005)

Effective linear programming based placement methods. - Sherief Reda; Amit Chowdhary (ISPD, 2006)

A tale of two nets: studies of wirelength progression in physical design. - Andrew B. Kahng; Sherief Reda (SLIP, 2006)

Computer-Aided Optimization of DNA Array Design and Manufacturing. - Andrew B. Kahng; Ion I. Mandoiu; Sherief Reda; Xu Xu 001; Alexander Zelikovsky (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

New and improved BIST diagnosis methods from combinatorial Group testing theory. - Andrew B. Kahng; Sherief Reda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Wirelength minimization for min-cut placements via placement feedback. - Andrew B. Kahng; Sherief Reda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking. - Andrew B. Kahng; Sherief Reda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A Fast Hierarchical Quadratic Placement Algorithm. - Gi-Joon Nam; Sherief Reda; Charles J. Alpert; Paul Villarrubia; Andrew B. Kahng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

APlace: A High Quality, Large-Scale Analytical Placer. - Andrew B. Kahng; Sherief Reda; Qinke Wang (Modern Circuit Placement, 2007)

Strategies for improving the parametric yield and profits of 3D ICs. - Cesare Ferri; Sherief Reda; R. Iris Bahar (ICCAD, 2007)

Hardware libraries: An architecture for economic acceleration in soft multi-core environments. - David Meisner; Sherief Reda (ICCD, 2007)

On-Line Adjustable Buffering for Runtime Power Reduction. - Andrew B. Kahng; Sherief Reda; Puneet Sharma (ISQED, 2007)

Within-die process variations: How accurately can they be statistically modeled? - Brendan Hargreaves; Henrik Hult; Sherief Reda (ASP-DAC, 2008)

Frequency and voltage planning for multi-core processors under thermal constraints. - Michael Kadin; Sherief Reda (ICCD, 2008)

Frequency planning for multi-core processors under thermal constraints. - Michael Kadin; Sherief Reda (ISLPED, 2008)

Parametric yield management for 3D ICs: Models and strategies for improvement. - Cesare Ferri; Sherief Reda; R. Iris Bahar (ACM J. Emerg. Technol. Comput. Syst., 2008)

Spectral techniques for high-resolution thermal characterization with limited sensor data. - Ryan Cochran; Sherief Reda (DAC, 2009)

Analyzing the impact of process variations on parametric measurements: Novel models and applications. - Sherief Reda; Sani R. Nassif (DATE, 2009)

High-performance, cost-effective heterogeneous 3D FPGA architectures. - Roto Le; Sherief Reda; R. Iris Bahar (FPGA, 2009)

Central vs. distributed dynamic thermal management for multi-core processors: which one is better? - Michael Kadin; Sherief Reda; Augustus K. Uht (ACM Great Lakes Symposium on VLSI, 2009)

Reducing the leakage and timing variability of 2D ICcs using 3D ICs. - Sherief Reda; Aung Si; R. Iris Bahar (ISLPED, 2009)

Using circuit structural analysis techniques for networks in systems biology. - Sherief Reda (SLIP, 2009)

Maximizing the Functional Yield of Wafer-to-Wafer 3-D Integration. - Sherief Reda; Gregory Smith 002; Larry Smith 004 (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Early estimation of TSV area for power delivery in 3-D integrated circuits. - Nauman H. Khan; Sherief Reda; Soha Hassoun (3DIC, 2010)

Consistent runtime thermal prediction and control through workload phase detection. - Ryan Cochran; Sherief Reda (DAC, 2010)

Thermal monitoring of real processors: techniques for sensor allocation and full characterization. - Abdullah Nazma Nowroz; Ryan Cochran; Sherief Reda (DAC, 2010)

Post-silicon power characterization using thermal infrared emissions. - Ryan Cochran; Abdullah Nazma Nowroz; Sherief Reda (ISLPED, 2010)

Fast, accurate a priori routing delay estimation. - Jinhai Qiu; Sherief Reda; Soha Hassoun (SLIP, 2010)

Improved post-silicon power modeling using AC lock-in techniques. - Abdullah Nazma Nowroz; Gary L. Woods; Sherief Reda (DAC, 2011)

Thermal and power characterization of field-programmable gate arrays. - Abdullah Nazma Nowroz; Sherief Reda (FPGA, 2011)

Identifying the optimal energy-efficient operating points of parallel workloads. - Ryan Cochran; Can Hankendi; Ayse K. Coskun; Sherief Reda (ICCAD, 2011)

Pack & Cap: adaptive DVFS and thread packing under power caps. - Ryan Cochran; Can Hankendi; Ayse K. Coskun; Sherief Reda (MICRO, 2011)

Thermal and Power Characterization of Real Computing Devices. - Sherief Reda (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

Improved Thermal Tracking for Processors Using Hard and Soft Sensor Allocation Techniques. - Sherief Reda; Ryan Cochran; Abdullah Nazma Nowroz (IEEE Trans. Computers, 2011)

Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators. - Kumud Nepal; Onur Ulusel; R. Iris Bahar; Sherief Reda (FCCM, 2012)

Temperature-aware computing: Achievements and remaining challenges. - Dhireesha Kudithipudi; Ayse K. Coskun; Sherief Reda; Qinru Qiu (IGCC, 2012)

Power Modeling and Characterization of Computing Devices: A Survey. - Sherief Reda; Abdullah Nazma Nowroz (Found. Trends Electron. Des. Autom., 2012)

Adaptive Power Capping for Servers with Multithreaded Workloads. - Sherief Reda; Ryan Cochran; Ayse K. Coskun (IEEE Micro, 2012)

Thermal prediction and adaptive control through workload phase detection. - Ryan Cochran; Sherief Reda (ACM Trans. Design Autom. Electr. Syst., 2012)

High-throughput TSV testing and characterization for 3D integration using thermal mapping. - Kapil Dev; Gary L. Woods; Sherief Reda (DAC, 2013)

Techniques for energy-efficient power budgeting in data centers. - Xin Zhan; Sherief Reda (DAC, 2013)

High-sensitivity hardware trojan detection using multimodal characterization. - Kangqiao Hu; Abdullah Nazma Nowroz; Sherief Reda; Farinaz Koushanfar (DATE, 2013)

Mitigating dark-silicon problems using superlattice-based thermoelectric coolers. - Francesco Paterna; Sherief Reda (DATE, 2013)

Power mapping and modeling of multi-core processors. - Kapil Dev; Abdullah Nazma Nowroz; Sherief Reda (ISLPED, 2013)

vCap: Adaptive power capping for virtualized servers. - Can Hankendi; Sherief Reda; Ayse K. Coskun (ISLPED, 2013)

Post-silicon power mapping techniques for integrated circuits. - Sherief Reda; Abdullah Nazma Nowroz; Ryan Cochran; Stefan Angelevski (Integr., 2013)

Power Mapping of Integrated Circuits Using AC-Based Thermography. - Abdullah Nazma Nowroz; Gary L. Woods; Sherief Reda (IEEE Trans. Very Large Scale Integr. Syst., 2013)

ABACUS: A technique for automated behavioral synthesis of approximate computing circuits. - Kumud Nepal; Yueting Li; R. Iris Bahar; Sherief Reda (DATE, 2014)

Thermal-aware layout planning for heterogeneous datacenters. - Reza Azimi; Xin Zhan; Sherief Reda (ISLPED, 2014)

Novel Techniques for High-Sensitivity Hardware Trojan Detection Using Thermal and Power Maps. - Abdullah Nazma Nowroz; Kangqiao Hu; Farinaz Koushanfar; Sherief Reda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators. - Onur Ulusel; Kumud Nepal; R. Iris Bahar; Sherief Reda (ACM Trans. Reconfigurable Technol. Syst., 2014)

DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications. - Soheil Hashemi; R. Iris Bahar; Sherief Reda (ICCAD, 2015)

How Good Are Low-Power 64-Bit SoCs for Server-Class Workloads? - Reza Azimi; Xin Zhan; Sherief Reda (IISWC, 2015)

Making sense of thermoelectrics for processor thermal management and energy harvesting. - Sriram Jayakumar; Sherief Reda (ISLPED, 2015)

Power Budgeting Techniques for Data Centers. - Xin Zhan; Sherief Reda (IEEE Trans. Computers, 2015)

DiBA: Distributed Power Budget Allocation for Large-Scale Computing Clusters. - Masoud Badiei; Xin Zhan; Reza Azimi; Sherief Reda; Na Li 002 (CCGrid, 2016)

Creating Soft Heterogeneity in Clusters Through Firmware Re-configuration. - Xin Zhan; Mohammed Shoaib; Sherief Reda (CCGrid, 2016)

Runtime configurable deep neural networks for energy-accuracy trade-off. - Hokchhay Tann; Soheil Hashemi; R. Iris Bahar; Sherief Reda (CODES+ISSS, 2016)

A low-power dynamic divider for approximate applications. - Soheil Hashemi; R. Iris Bahar; Sherief Reda (DAC, 2016)

Scheduling Challenges and Opportunities in Integrated CPU+GPU Processors. - Kapil Dev; Sherief Reda (ESTIMedia, 2016)

Hardware acceleration of feature detection and description algorithms on low-power embedded platforms. - Onur Ulusel; Christopher B. Picardo; Christopher B. Harris; Sherief Reda; R. Iris Bahar (FPL, 2016)

Power-aware characterization and mapping of workloads on CPU-GPU processors. - Kapil Dev; Xin Zhan; Sherief Reda (IISWC, 2016)

Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs. - Kapil Dev; Sherief Reda; Indrani Paul; Wei Huang 004; Wayne P. Burleson (ISVLSI, 2016)

Understanding the Role of GPGPU-Accelerated SoC-Based ARM Clusters. - Reza Azimi; Tyler Fox; Sherief Reda (CLUSTER, 2017)

Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks. - Hokchhay Tann; Soheil Hashemi; R. Iris Bahar; Sherief Reda (DAC, 2017)

Understanding the impact of precision quantization on the accuracy and energy of neural networks. - Soheil Hashemi; Nicholas Anthony; Hokchhay Tann; R. Iris Bahar; Sherief Reda (DATE, 2017)

Blind identification of power sources in processors. - Sherief Reda; Adel Belouchrani (DATE, 2017)

Fast Decentralized Power Capping for Server Clusters. - Reza Azimi; Masoud Badiei; Xin Zhan; Na Li 002; Sherief Reda (HPCA, 2017)

LACore: A Supercomputing-Like Linear Algebra Accelerator for SoC-Based Designs. - Samuel Steffl; Sherief Reda (ICCD, 2017)

CloudV: A cloud-based educational digital design environment. - Mohamed Shalan; Sherief Reda (MSE, 2017)

CARB: A C-State Power Management Arbiter for Latency-Critical Workloads. - Xin Zhan; Reza Azimi; Svilen Kanev; David M. Brooks; Sherief Reda (IEEE Comput. Archit. Lett., 2017)

Scheduling on CPU + GPU Processors Under Dynamic Conditions. - Kapil Dev; Xin Zhan; Sherief Reda (J. Low Power Electron., 2017)

BLASYS: approximate logic synthesis using boolean matrix factorization. - Soheil Hashemi; Hokchhay Tann; Sherief Reda (DAC, 2018)

Approximate computing for biometrie security systems: A case study on iris scanning. - Soheil Hashemi; Hokchhay Tann; Francesco Buttafuoco; Sherief Reda (DATE, 2018)

QoR-aware power capping for approximate big data processing. - Seyed Morteza Nabavinejad; Xin Zhan; Reza Azimi; Maziar Goudarzi; Sherief Reda (DATE, 2018)

PowerCoord: A Coordinated Power Capping Controller for Multi-CPU/GPU Servers. - Reza Azimi; Chao Jing; Sherief Reda (IGSC, 2018)

Understanding the Sources of Power Consumption in Mobile SoCs. - Mostafa Said; Sofiane Chetoui; Adel Belouchrani; Sherief Reda (IGSC, 2018)

Parallelized Linear Classification with Volumetric Chemical Perceptrons. - Christopher E. Arcadia; Hokchhay Tann; Amanda Dombroski; Kady Ferguson; Shui Ling Chen; Eunsuk Kim; Christopher Rose; Brenda M. Rubenstein; Sherief Reda; Jacob K. Rosenstein (ICRC, 2018)

Computing with Chemicals: Perceptrons Using Mixtures of Small Molecules. - Christopher Rose; Sherief Reda; Brenda M. Rubenstein; Jacob K. Rosenstein (ISIT, 2018)

Flexible Deep Neural Network Processing. - Hokchhay Tann; Soheil Hashemi; Sherief Reda (CoRR, 2018)

Implications of Integrated CPU-GPU Processors on Thermal and Power Management Techniques. - Kapil Dev; Indrani Paul; Wei Huang 004; Yasuko Eckert; Wayne P. Burleson; Sherief Reda (CoRR, 2018)

Scale-Out vs Scale-Up: A Study of ARM-based SoCs on Server-Class Workloads. - Reza Azimi; Tyler Fox; Wendy Gonzalez; Sherief Reda (ACM Trans. Model. Perform. Evaluation Comput. Syst., 2018)

Approximate Multipliers and Dividers Using Dynamic Bit Selection. - Soheil Hashemi; Sherief Reda (Approximate Circuits, 2019)

Approximate Logic Synthesis Using Boolean Matrix Factorization. - Soheil Hashemi; Hokchhay Tann; Sherief Reda (Approximate Circuits, 2019)

Approximate Computing for Iris Recognition Systems. - Hokchhay Tann; Soheil Hashemi; Francesco Buttafuoco; Sherief Reda (Approximate Circuits, 2019)

Lightweight Deep Neural Network Accelerators Using Approximate SW/HW Techniques. - Hokchhay Tann; Soheil Hashemi; Sherief Reda (Approximate Circuits, 2019)

Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project. - Tutu Ajayi; Vidya A. Chhabria; Mateus Fogaça; Soheil Hashemi; Abdelrahman Hosny; Andrew B. Kahng; Minsoo Kim; Jeongsup Lee; Uday Mallappa; Marina Neseem; Geraldo Pradipta; Sherief Reda; et al. (DAC, 2019)

Generalized Matrix Factorization Techniques for Approximate Logic Synthesis. - Soheil Hashemi; Sherief Reda (DATE, 2019)

Modeling and Optimization of Chip Cooling with Two-Phase Vapor Chambers. - Zihao Yuan; Geoffrey Vaartstra; Prachi Shukla; Sherief Reda; Evelyn Wang; Ayse K. Coskun (ISLPED, 2019)

Coordinated DVFS and Precision Control for Deep Neural Networks. - Seyed Morteza Nabavinejad; Hassan Hafez-Kolahi; Sherief Reda (IEEE Comput. Archit. Lett., 2019)

Principles of Information Storage in Small-Molecule Mixtures. - Jacob K. Rosenstein; Christopher Rose; Sherief Reda; Peter M. Weber; Eunsuk Kim; Jason Sello; Joseph Geiser; Eamonn Kennedy; Christopher E. Arcadia; Amanda Dombroski; Kady Oakley; Shui Ling Chen; et al. (CoRR, 2019)

Automated High-Level Generation of Low-Power Approximate Computing Circuits. - Kumud Nepal; Soheil Hashemi; Hokchhay Tann; R. Iris Bahar; Sherief Reda (IEEE Trans. Emerg. Top. Comput., 2019)

DRiLLS: Deep Reinforcement Learning for Logic Synthesis. - Abdelrahman Hosny; Soheil Hashemi; Mohamed Shalan; Sherief Reda (ASP-DAC, 2020)

ApproxDNN: Incentivizing DNN Approximation in Cloud. - Seyed Morteza Nabavinejad; Lena Mashayekhy; Sherief Reda (CCGRID, 2020)

AdaSense: Adaptive Low-Power Sensing and Activity Recognition for Wearable Devices. - Marina Neseem; Jon Nelson; Sherief Reda (DAC, 2020)

A Learning-Based Thermal Simulation Framework for Emerging Two-Phase Cooling Technologies. - Zihao Yuan; Geoffrey Vaartstra; Prachi Shukla; Zhengmao Lu; Evelyn Wang; Sherief Reda; Ayse K. Coskun (DATE, 2020)

Overview of the OpenROAD Digital Design Flow from RTL to GDS. - Sherief Reda (VLSI-DAT, 2020)

Temperature and Supply Voltage Monitoring with Current-mode Relaxation Oscillators. - Shanshan Dai; Caleb R. Tulloss; Xiaoyu Lian; Kangping Hu; Sherief Reda; Jacob K. Rosenstein (VLSI-SOC, 2020)

Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring. - Shanshan Dai; Caleb R. Tulloss; Xiaoyu Lian; Kangping Hu; Sherief Reda; Jacob K. Rosenstein (VLSI-SoC (Selected Papers), 2020)

Simultaneous Estimation of Temperature and Voltage from Digital Delay Diversity. - Xiaoyu Lian; Sherief Reda; Jacob K. Rosenstein (VLSI-SOC, 2020)

Dual-precision fixed-point arithmetic for low-power ray-triangle intersections. - Krishna Rajan; Soheil Hashemi; Ulya R. Karpuzcu; Michael C. Doggett; Sherief Reda (Comput. Graph., 2020)

Coordinated Self-Tuning Thermal Management Controller for Mobile Devices. - Sofiane Chetoui; Sherief Reda (IEEE Des. Test, 2020)

A Resource-Efficient Embedded Iris Recognition System Using Fully Convolutional Networks. - Hokchhay Tann; Heng Zhao; Sherief Reda (ACM J. Emerg. Technol. Comput. Syst., 2020)

Approximate Logic Synthesis: A Survey. - Ilaria Scarabottolo; Giovanni Ansaloni; George A. Constantinides; Laura Pozzi 001; Sherief Reda (Proc. IEEE, 2020)

PowerCoord: Power capping coordination for multi-CPU/GPU servers using reinforcement learning. - Reza Azimi; Chao Jing; Sherief Reda (Sustain. Comput. Informatics Syst., 2020)

LoCool: Fighting Hot Spots Locally for Improving System Energy Efficiency. - Fulya Kaplan; Mostafa Said; Sherief Reda; Ayse K. Coskun (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

BatchSizer: Power-Performance Trade-off for DNN Inference. - Seyed Morteza Nabavinejad; Sherief Reda; Masoumeh Ebrahimi (ASP-DAC, 2021)

Workload- and User-aware Battery Lifetime Management for Mobile SoCs. - Sofiane Chetoui; Sherief Reda (DATE, 2021)

AdaCon: Adaptive Context-Aware Object Detection for Resource-Constrained Embedded Devices. - Marina Neseem; Sherief Reda (ICCAD, 2021)

Sparse Bitmap Compression for Memory-Efficient Training on the Edge. - Abdelrahman Hosny; Marina Neseem; Sherief Reda (SEC, 2021)

BayesTuner: Leveraging Bayesian Optimization For DNN Inference Configuration Selection. - Seyed Morteza Nabavinejad; Sherief Reda (IEEE Comput. Archit. Lett., 2021)

BitTrain: Sparse Bitmap Compression for Memory-Efficient Training on the Edge. - Abdelrahman Hosny; Marina Neseem; Sherief Reda (CoRR, 2021)

Guest Editors' Introduction: The Resurgence of Open- Source EDA Technology. - Sherief Reda; Leon Stok; Pierre-Emmanuel Gaillardon (IEEE Des. Test, 2021)

ARBench: Augmented Reality Benchmark For Mobile Devices. - Sofiane Chetoui; Rahul Shahi; Seif Abdelaziz; Abhinav Golas; Farrukh Hijaz; Sherief Reda (ISPASS, 2022)

Alternating Blind Identification of Power Sources for Mobile SoCs. - Sofiane Chetoui; Michael Chen; Abhinav Golas; Farrukh Hijaz; Adel Belouchrani; Sherief Reda (ICPE, 2022)

ISLPED 2021: The 25th Anniversary! - Yiran Chen 001; Sherief Reda (IEEE Des. Test, 2022)

CasCon: Cascaded Thermal and Electrical Current Throttling for Mobile Devices. - Sofiane Chetoui; Sherief Reda (IEEE Embed. Syst. Lett., 2022)

Characterizing and Optimizing EDA Flows for the Cloud. - Abdelrahman Hosny; Sherief Reda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Approximate Logic Synthesis Using Boolean Matrix Factorization. - Jingxiao Ma; Soheil Hashemi; Sherief Reda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

PACT: An Extensible Parallel Thermal Simulator for Emerging Integration and Cooling Technologies. - Zihao Yuan; Prachi Shukla; Sofiane Chetoui; Sean S. Nemtzow; Sherief Reda; Ayse K. Coskun (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Coordinated Batching and DVFS for DNN Inference on GPU Accelerators. - Seyed Morteza Nabavinejad; Sherief Reda; Masoumeh Ebrahimi (IEEE Trans. Parallel Distributed Syst., 2022)

RUCA: RUntime Configurable Approximate Circuits with Self-Correcting Capability. - Jingxiao Ma; Sherief Reda (ASP-DAC, 2023)

Microscale 3-D Capacitance Tomography with a CMOS Sensor Array. - Manar Abdelatty; Joseph Incandela; Kangping Hu; Joseph W. Larkin; Sherief Reda; Jacob K. Rosenstein (BioCAS, 2023)

AdaMTL: Adaptive Input-dependent Inference for Efficient Multi-Task Learning. - Marina Neseem; Ahmed Agiza; Sherief Reda (CVPR Workshops, 2023)

GraPhSyM: Graph Physical Synthesis Model. - Ahmed Agiza; Rajarshi Roy 003; Teodor-Dumitru Ene; Saad Godil; Sherief Reda; Bryan Catanzaro (ICCAD, 2023)

WeNet: Configurable Neural Network with Dynamic Weight-Enabling for Efficient Inference. - Jingxiao Ma; Sherief Reda (ISLPED, 2023)

Throughput Maximization of DNN Inference: Batching or Multi-Tenancy? - Seyed Morteza Nabavinejad; Masoumeh Ebrahimi; Sherief Reda (CoRR, 2023)

MediatorDNN: Contention Mitigation for Co-Located DNN Inference Jobs. - Seyed Morteza Nabavinejad; Sherief Reda; Tian Guo 001 (CLOUD, 2024)

FairCIM: Fair Interference Mitigation by DNN Switching for Latency-Sensitive Inference Jobs. - Seyed Morteza Nabavinejad; Sherief Reda; Tian Guo 001 (ACSOS, 2024)

PoliTune: Analyzing the Impact of Data Selection and Fine-Tuning on Economic and Political Biases in Large Language Models. - Ahmed Agiza; Mohamed Mostagir; Sherief Reda (AIES (1), 2024)

MTLoRA: A Low-Rank Adaptation Approach for Efficient Multi-Task Learning. - Ahmed Agiza; Marina Neseem; Sherief Reda (CVPR, 2024)

PikeLPN: Mitigating Overlooked Inefficiencies of Low-Precision Neural Networks. - Marina Neseem; Conor McCullough; Randy Hsin; Chas Leichner; Shan Li 001; In Suk Chong; Andrew G. Howard; Lukasz Lew; Sherief Reda; Ville-Mikko Rautio; Daniele Moro (CVPR, 2024)

torchmSAT: A GPU-Accelerated Approximation To The Maximum Satisfiability Problem. - Abdelrahman Hosny; Sherief Reda (CoRR, 2024)

Analyzing the Impact of Data Selection and Fine-Tuning on Economic and Political Biases in LLMs. - Ahmed Agiza; Mohamed Mostagir; Sherief Reda (CoRR, 2024)

HDLCopilot: Hardware Design Library Querying with Natural Language. - Manar Abdelatty; Sherief Reda (CoRR, 2024)

Automatic MILP solver configuration by learning problem similarities. - Abdelrahman Hosny; Sherief Reda (Ann. Oper. Res., 2024)

Electrical Capacitance Tomography of Cell Cultures on a CMOS Microelectrode Array. - Manar Abdelatty; Joseph Incandela; Kangping Hu; Pushkaraj S. Joshi; Joseph W. Larkin; Sherief Reda; Jacob K. Rosenstein (IEEE Trans. Biomed. Circuits Syst., 2024)

MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs. - Manar Abdelatty; Jingxiao Ma; Sherief Reda (ASP-DAC, 2025)

Fast Machine Learning Based Prediction for Temperature Simulation Using Compact Models. - Mohammadamin Hajikhodaverdian; Sherief Reda; Ayse K. Coskun (DATE, 2025)

FF-INT8: Efficient Forward-Forward DNN Training on Edge Devices with INT8 Precision. - Jingxiao Ma; Priyadarshini Panda; Sherief Reda (CoRR, 2025)

Approximate Logic Synthesis Using BLASYS. - Jingxiao Ma; Soheil Hashemi; Sherief Reda (CoRR, 2025)