A Fully Integrated 4 × 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 µm CMOS SOI Technology. - Adithyaram Narasimha; Behnam Analui; Yi Liang; Thomas J. Sleboda; Sherif Abdalla; Erwin Balmater; Steffen Gloeckner; Drew Guckenberger; Mark Harrison; Roger G. M. P. Koumans; Daniel Kucharski; Attila Mekis; et al. (IEEE J. Solid State Circuits, 2007)

10Gb/s 15mW optical receiver with integrated Germanium photodetector and hybrid inductor peaking in 0.13µm SOI CMOS technology. - Daniel Kucharski; Drew Guckenberger; Gianlorenzo Masini; Sherif Abdalla; Jeremy Witzens; Subal Sahni (ISSCC, 2010)

19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC. - Fazil Ahmad; Greg Unruh; Amrutha Iyer; Pin-En Su; Sherif Abdalla; Bo Shen; Mark Chambers; Ichiro Fujimori (ISSCC, 2016)

A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling. - Fazil Ahmad; Greg Unruh; Amrutha Iyer; Pin-En Su; Sherif Abdalla; Bo Shen; Mark Chambers; Ichiro Fujimori (IEEE J. Solid State Circuits, 2017)