DFM/DFY practices during physical designs for timing, signal integrity, and power. - Shi-Hao Chen; Ke-Cheng Chu; Jiing-Yuan Lin; Cheng-Hong Tsai (ASP-DAC, 2007)

Experiences of low power design implementation and verification. - Shi-Hao Chen; Jiing-Yuan Lin (ASP-DAC, 2008)

Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs. - Szu-Pang Mu; Yi-Ming Wang; Hao-Yu Yang; Mango Chia-Tso Chao; Shi-Hao Chen; Chih-Mou Tseng; Tsung-Ying Tsai (ICCAD, 2010)

An Efficient Hamiltonian-cycle power-switch routing for MTCMOS designs. - Yi-Ming Wang; Shi-Hao Chen; Mango Chia-Tso Chao (ASP-DAC, 2012)

On effective flip-chip routing via pseudo single redistribution layer. - Hsin-Wu Hsu; Meng-Ling Chen; Hung-Ming Chen; Hung-Chun Li; Shi-Hao Chen (DATE, 2012)

Testing retention flip-flops in power-gated designs. - Hao-Wen Hsu; Shih-Hua Kuo; Wen-Hsiang Chang; Shi-Hao Chen; Ming-Tung Chang; Mango Chia-Tso Chao (VTS, 2013)

Power-Up Sequence Control for MTCMOS Designs. - Shi-Hao Chen; Youn-Long Lin; Mango Chia-Tso Chao (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Routability-driven bump assignment for chip-package co-design. - Meng-Ling Chen; Tu-Hsiung Tsai; Hung-Ming Chen; Shi-Hao Chen (ASP-DAC, 2014)

Cost-effective decap selection for beyond die power integrity. - Yi-En Chen; Tu-Hsiung Tsai; Shi-Hao Chen; Hung-Ming Chen (DATE, 2014)

Power-switch routing for reducing dynamic IR drop in multi-domain MTCMOS designs. - Yi-Ming Wang; Mango Chia-Tso Chao; Shi-Hao Chen; Hung-Chun Li (VLSI-DAT, 2014)

Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer. - Wen-Hsiang Chang; Mango Chia-Tso Chao; Shi-Hao Chen (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators. - Szu-Pang Mu; Mango C.-T. Chao; Shi-Hao Chen; Yi-Ming Wang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM. - Jheng-Yi Chen; Ming-Yu Chang; Shi-Hao Chen; Jia-Wei Lee; Meng-Hsueh Chiang (ISQED, 2018)

DVFS Binning Using Machine-Learning Techniques. - Keng-Wei Chang; Chun-Yang Huang; Szu-Pang Mu; Jian-Min Huang; Shi-Hao Chen; Mango C.-T. Chao (ITC-Asia, 2018)

Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs. - Yu-Zhe Wang; Jingjie Wu; Shi-Hao Chen; Mango Chia-Tso Chao; Chia-Hsiang Yang (VLSI-DAT, 2019)

Application of Generative Adversarial Networks for Virtual Silicon Data Generation and Design-Technology Co-Optimization: A Study on WAT and CP. - Shih-Nung Chen; Shi-Hao Chen (IEEE Access, 2024)

A 28-nm 1.3-mW Speech-to-Text Accelerator for Edge AI Devices. - Yu-Hsuan Tsai; Yi-Cheng Lin; Wen-Ching Chen; Liang-Yi Lin; Nian-Shyang Chang; Chun-Pin Lin; Shi-Hao Chen; Chi-Shi Chen; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2024)