Fault emulation: a new approach to fault grading. - Kwang-Ting Cheng; Shi-Yu Huang; Wei-Jin Dai (ICCAD, 1995)

Error Correction Based on Verification Techniques. - Shi-Yu Huang; Kuang-Chien Chen; Kwang-Ting Cheng (DAC, 1996)

Compact Vector Generation for Accurate Power Simulation. - Shi-Yu Huang; Kuang-Chien Chen; Kwang-Ting Cheng; Tien-Chien Lee (DAC, 1996)

On Verifying the Correctness of Retimed Circuits. - Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen (Great Lakes Symposium on VLSI, 1996)

A novel methodology for transistor-level power estimation. - Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen; Mike Tien-Chien Lee (ISLPED, 1996)

An ATPG-Based Framework for Verifying Sequential Equivalence. - Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen; Uwe Gläser (ITC, 1996)

AQUILA: An equivalence verifier for large sequential circuits. - Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen (ASP-DAC, 1997)

Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. - Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen; David Ihsin Cheng (ITC, 1997)

Incremental logic rectification. - Shi-Yu Huang; Kuang-Chien Chen; Kwang-Ting Cheng (VTS, 1997)

A Hybrid Power Model for RTL Power Estimation. - Yi-Min Jiang; Shi-Yu Huang; Kwang-Ting Cheng; Deborah C. Wang; ChingYen Ho (ASP-DAC, 1998)

Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. - Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen; Juin-Yeu Joseph Lu (DAC, 1998)

Fault emulation: A new methodology for fault grading. - Kwang-Ting Cheng; Shi-Yu Huang; Wei-Jin Dai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

ErrorTracer: design error diagnosis based on fault simulation techniques. - Shi-Yu Huang; Kwang-Ting Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

AutoFix: a hybrid tool for automatic logic rectification. - Shi-Yu Huang; Kuang-Chien Chen; Kwang-Ting Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

High Performance/Delay Testing. - Shi-Yu Huang; Sudhakar M. Reddy (Asian Test Symposium, 2000)

AQUILA: An Equivalence Checking System for Large Sequential Designs. - Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen; Chung-Yang Huang; Forrest Brewer (IEEE Trans. Computers, 2000)

Towards the logic defect diagnosis for partial-scan designs. - Shi-Yu Huang (ASP-DAC, 2001)

On speeding up extended finite state machines using catalyst circuitry. - Shi-Yu Huang (ASP-DAC, 2001)

A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. - Chih-Wea Wang; Ruey-Shing Tzeng; Chi-Feng Wu; Chih-Tsun Huang; Cheng-Wen Wu; Shi-Yu Huang; Shyh-Horng Lin; Hsin-Po Wang 002 (Asian Test Symposium, 2001)

On Improving the Accuracy Of Multiple Defect Diagnosis. - Shi-Yu Huang (VTS, 2001)

Verifying sequential equivalence using ATPG techniques. - Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen (ACM Trans. Design Autom. Electr. Syst., 2001)

Diagnosis Of Byzantine Open-Segment Faults. - Shi-Yu Huang (Asian Test Symposium, 2002)

Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm. - Horng-Bin Wang; Shi-Yu Huang; Jing-Reng Huang (DFT, 2002)

Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation. - Shi-Yu Huang (VTS, 2002)

Improving the Timing of Extended Finite State Machines Via Catalyst. - Shi-Yu Huang (VLSI Design, 2002)

Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults. - Yu-Chiun Lin; Shi-Yu Huang (Asian Test Symposium, 2003)

Decomposition of Extended Finite State Machine for Low Power Design. - MingHung Lee; TingTing Hwang; Shi-Yu Huang (DATE, 2003)

Combinational circuit fault diagnosis using logic emulation. - Shyue-Kung Lu; Jian-Long Chen; Cheng-Wen Wu; Ken-Feng Chang; Shi-Yu Huang (ISCAS (5), 2003)

A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis. - Shi-Yu Huang (J. Electron. Test., 2003)

Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults. - Hong-Chou Kao; Ming-Fu Tsai; Shi-Yu Huang; Cheng-Wen Wu; Wen-Feng Chang; Shyue-Kung Lu (J. Inf. Sci. Eng., 2003)

A Fading Algorithm For Sequential Fault Diagnosis. - Shi-Yu Huang (DFT, 2004)

Power estimation starategies for a low-power security processor. - Yen-Fong Lee; Shi-Yu Huang; Sheng-Yu Hsu; I-Ling Chen; Cheng-Tao Shieh; Jian-Cheng Lin; Shih-Chieh Chang (ASP-DAC, 2005)

Quick Scan Chain Diagnosis Using Signal Profiling. - Jheng-Syun Yang; Shi-Yu Huang (ICCD, 2005)

A low-power SRAM design using quiet-bitline architecture. - Shin-Pao Cheng; Shi-Yu Huang (MTDT, 2005)

Low-cost logarithmic CMOS image sensing by nonlinear analog-to-digital conversion. - Ying-Chieh Chuang; Shih-Fang Chen; Shi-Yu Huang; Ya-Chin King (IEEE Trans. Consumer Electron., 2005)

A network security processor design based on an integrated SOC design and test platform. - Chen-Hsing Wang; Chih-Yen Lo; Min-Sheng Lee; Jen-Chieh Yeh; Chih-Tsun Huang; Cheng-Wen Wu; Shi-Yu Huang (DAC, 2006)

Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults. - Yu-Chiun Lin; Shi-Yu Huang (J. Electron. Test., 2006)

Built-In Speed Grading with a Process-Tolerant ADPLL. - Hsuan-Jung Hsu; Chun-Chieh Tu; Shi-Yu Huang (ATS, 2007)

RT-level vector selection for realistic peak power simulation. - Chia-Chien Weng; Ching-Shang Yang; Shi-Yu Huang (ACM Great Lakes Symposium on VLSI, 2007)

Robust paradigm for diagnosing hold-time faults in scan chains. - Chao-Wen Tzeng; J.-J. Hsu; Shi-Yu Huang (IET Comput. Digit. Tech., 2007)

Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in a Scan Chain. - Chao-Wen Tzeng; Shi-Yu Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Two-Gear Low-Power Scan Test. - Chao-Wen Tzeng; Shi-Yu Huang (ATS, 2008)

UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting. - Chao-Wen Tzeng; Shi-Yu Huang (IEEE Des. Test Comput., 2008)

X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs. - Ya-Chun Lai; Shi-Yu Huang (IEEE J. Solid State Circuits, 2008)

A Resilient and Power-Efficient Automatic-Power-Down Sense Amplifier for SRAM Design. - Ya-Chun Lai; Shi-Yu Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A low-power SRAM for Viterbi decoder in wireless communication. - Shin-Pao Cheng; Shi-Yu Huang (IEEE Trans. Consumer Electron., 2008)

A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques. - Chao-Wen Tzeng; Jheng-Syun Yang; Shi-Yu Huang (ACM Trans. Design Autom. Electr. Syst., 2008)

QC-Fill: An X-Fill method for quick-and-cool scan test. - Chao-Wen Tzeng; Shi-Yu Huang (DATE, 2009)

Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT). - Ya-Chun Lai; Shi-Yu Huang (IEEE J. Solid State Circuits, 2009)

Resilient Self-VDD-Tuning Scheme With Speed-Margining for Low-Power SRAM. - Ya-Chun Lai; Shi-Yu Huang; Hsuan-Jung Hsu (IEEE J. Solid State Circuits, 2009)

Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects. - Chao-Wen Tzeng; Han-Chia Cheng; Shi-Yu Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test. - Chao-Wen Tzeng; Shi-Yu Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

PAC duo system power estimation at ESL. - Wen-Tsan Hsieh; Jen-Chieh Yeh; Shi-Yu Huang (ASP-DAC, 2010)

Performance Characterization of TSV in 3D IC via Sensitivity Analysis. - Jhih-Wei You; Shi-Yu Huang; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (Asian Test Symposium, 2010)

Power aware SID-based simulator for embedded multicore DSP subsystems. - Cheng-Yen Lin; Po-Yu Chen; Chun-Kai Tseng; Chung-Wen Huang; Chia-Chieh Weng; Chi-Bang Kuan; Shih-Han Lin; Shi-Yu Huang; Jenq Kuen Lee (CODES+ISSS, 2010)

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. - Tsung-Yeh Li; Shi-Yu Huang; Hsuan-Jung Hsu; Chao-Wen Tzeng; Chih-Tsun Huang; Jing-Jia Liou; Hsi-Pin Ma; Po-Chiun Huang; Jenn-Chyou Bor; Cheng-Wen Wu; Ching-Cheng Tien; Mike Wang (DFT, 2010)

Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture With Test Compression. - Chao-Wen Tzeng; Shi-Yu Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs. - Chen-Wei Hsu; Jia-Lu Liao; Shan-Chien Fang; Chia-Chien Weng; Shi-Yu Huang; Wen-Tsan Hsieh; Jen-Chieh Yeh (DAC, 2011)

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. - Chin-Fu Li; Chi-Ying Lee; Chen-Hsing Wang; Shu-Lin Chang; Li-Ming Denq; Chun-Chuan Chi; Hsuan-Jung Hsu; Ming-Yi Chu; Jing-Jia Liou; Shi-Yu Huang; Po-Chiun Huang; Hsi-Pin Ma; et al. (DAC, 2011)

Black-box leakage power modeling for cell library and SRAM compiler. - Chun-Kai Tseng; Shi-Yu Huang; Chia-Chien Weng; Shan-Chien Fang; Ji-Jan Chen (DATE, 2011)

A fully cell-based design for timing measurement of memory. - Yi-Chung Chang; Shi-Yu Huang; Chao-Wen Tzeng; Jack T. Yao (ITC, 2011)

Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores. - Shyue-Kung Lu; Yin Chen; Shi-Yu Huang; Cheng Wu (IEEE Des. Test Comput., 2011)

A Light-and-Fast SLAM Algorithm for Robots in Indoor Environments Using Line Segment Map. - Bor-Woei Kuo; Hsun-Hao Chang; Yung-Chang Chen; Shi-Yu Huang (J. Robotics, 2011)

P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation. - Cheng-Hung Lo; Shi-Yu Huang (IEEE J. Solid State Circuits, 2011)

A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme. - Hsuan-Jung Hsu; Shi-Yu Huang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Programmable Leakage Test and Binning for TSVs. - Yu-Hsiang Lin; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng (Asian Test Symposium, 2012)

Small delay testing for TSVs in 3-D ICs. - Shi-Yu Huang; Yu-Hsiang Lin; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter; Yung-Fa Chou; Ding-Ming Kwai (DAC, 2012)

A unified method for parametric fault characterization of post-bond TSVs. - Yu-Hsiang Lin; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter (ITC, 2012)

Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property. - Ruo-Ting Ding; Shi-Yu Huang; Chao-Wen Tzeng; Shan-Chien Fang; Chia-Chien Weng (VLSI-DAT, 2012)

A UWB IR timed-array radar using time-shifted direct-sampling architecture. - Chang-Ming Lai; Kai-Wen Tan; Liu-Yuan Yu; Yen-Ju Chen; Jun-Wei Huang; Shr-Chau Lai; Feng-Hsu Chung; Chia-Fung Yen; Jen-Ming Wu; Po-Chiun Huang; Keh-Jeng Chang; Shi-Yu Huang; et al. (VLSIC, 2012)

High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction. - Feng-Cheng Huang; Shi-Yu Huang; Ji-Wei Ker; Yung-Chang Chen (IEEE Trans. Circuits Syst. Video Technol., 2012)

Mid-bond Interposer Wire Test. - Li-Ren Huang; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter (Asian Test Symposium, 2013)

At-speed BIST for interposer wires supporting on-the-spot diagnosis. - Shi-Yu Huang; Jeo-Yen Lee; Kun-Han Tsai; Wu-Tung Cheng (IOLTS, 2013)

Delay testing and characterization of post-bond interposer wires in 2.5-D ICs. - Shi-Yu Huang; Li-Ren Huang; Kun-Han Tsai; Wu-Tung Cheng (ITC, 2013)

Worst-case IR-drop monitoring with 1GHz sampling rate. - Chen-Hsiang Hsu; Shi-Yu Huang; Ding-Ming Kwai; Yung-Fa Chou (VLSI-DAT, 2013)

Oscillation-Based Prebond TSV Test. - Li-Ren Huang; Shi-Yu Huang; Stephen K. Sunter; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control. - Shi-Yu Huang; Yu-Hsiang Lin; Li-Ren Huang; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. - Yu-Hsiang Lin; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter; Yung-Fa Chou; Ding-Ming Kwai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism. - Ji-Wei Ker; Shi-Yu Huang; Chao-Wen Tzeng; Ding-Ming Kwai; Yung-Fa Chou (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping. - Pei-Ying Chao; Chao-Wen Tzeng; Shi-Yu Huang; Chia-Chieh Weng; Shan-Chien Fang (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Cell-Based Process Resilient Multiphase Clock Generation. - Ruo-Ting Ding; Shi-Yu Huang; Chao-Wen Tzeng (IEEE Trans. Very Large Scale Integr. Syst., 2013)

AC-Plus Scan Methodology for Small Delay Testing and Characterization. - Tsung-Yeh Li; Shi-Yu Huang; Hsuan-Jung Hsu; Chao-Wen Tzeng; Chih-Tsun Huang; Jing-Jia Liou; Hsi-Pin Ma; Po-Chiun Huang; Jenn-Chyou Bor; Ching-Cheng Tien; Chi-Hu Wang; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2013)

In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis. - Jhih-Wei You; Shi-Yu Huang; Yu-Hsiang Lin; Meng-Hsiu Tsai; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2013)

On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs. - Shi-Yu Huang; Hua-Xuan Li; Zeng-Fu Zeng; Kun-Han Tsai; Wu-Tung Cheng (ATS, 2014)

On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs. - Shi-Yu Huang; Zeng-Fu Zeng; Kun-Han Tsai; Wu-Tung Cheng (ETS, 2014)

PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning. - Shi-Yu Huang; Li-Ren Huang (IEEE Des. Test, 2014)

Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs. - Li-Ren Huang; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Pulse-Vanishing Test for Interposers Wires in 2.5-D IC. - Shi-Yu Huang; Jeo-Yen Lee; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration. - Chao-Wen Tzeng; Shi-Yu Huang; Pei-Ying Chao (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Temperature-aware online testing of power-delivery TSVs. - Hua-Cheng Fu; Shi-Yu Huang; Ding-Ming Kwai; Yung-Fa Chou (3DIC, 2015)

Cell-based programmable phase shifter design for pulsed radar SoC. - Jinn-Yann Liu; Shi-Yu Huang; Ta-Shun Chu (ASICON, 2015)

Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects. - Shi-Yu Huang; Meng-Ting Tsai; Kun-Han Hans Tsai; Wu-Tung Cheng (DATE, 2015)

Monitoring the delay of long interconnects via distributed TDC. - Meng-Ting Tsai; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng (ITC, 2015)

Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects. - Shi-Yu Huang; Meng-Ting Tsai; Hua-Xuan Li; Zeng-Fu Zeng; Kun-Han Hans Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects. - Shi-Yu Huang; Meng-Ting Tsai; Zeng-Fu Zeng; Kun-Han Hans Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems. - Cheng-Yen Lin; Chung-Wen Huang; Chi-Bang Kuan; Shi-Yu Huang; Jenq Kuen Lee (ACM Trans. Design Autom. Electr. Syst., 2015)

Pre-Bond and Post-Bond Testing of TSVs and Die-to-Die Interconnects. - Shi-Yu Huang (ATS, 2016)

Die-to-Die Clock Skew Characterization and Tuning for 2.5D ICs. - Shi-Yu Huang; Chih-Chieh Zheng (ATS, 2016)

Testing of small delay faults in a clock network. - Shaofu Yang; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng (ETS, 2016)

A wide-range clock signal generation scheme for speed grading of a logic core. - Shi-Yu Huang; Tzu-Heng Huang; Kun-Han Tsai; Wu-Tung Cheng (HPCS, 2016)

Cell-based delay locked loop compiler. - Pei-Ching Huang; Shi-Yu Huang (ISOCC, 2016)

Online slack-time binning for IO-registered die-to-die interconnects. - Chih-Chieh Zheng; Shi-Yu Huang; Shyue-Kung Lu; Ting-Chi Wang; Kun-Han Tsai; Wu-Tung Cheng (ITC, 2016)

Versatile Transition-Time Monitoring for Interconnects via Distributed TDC. - Shi-Yu Huang; Chih-Chieh Cheng; Meng-Ting Tsai; Kuan-Chen Huang; Kun-Han Tsai; Wu-Tung Cheng (IEEE Des. Test, 2016)

Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects. - Shi-Yu Huang; Meng-Ting Tsai; Kun-Han Tsai; Wu-Tung Cheng (IEEE Des. Test, 2016)

Cloud-Based PVT Monitoring System for IoT Devices. - Guan-Hao Lian; Shi-Yu Huang; Wei-yi Chen (ATS, 2017)

DLL-Assisted Clock Synchronization Method for Multi-Die ICs. - Chia-Yuan Cheng; Shi-Yu Huang; Ding-Ming Kwai; Yung-Fa Chou (ICCD, 2017)

Resilient Cell-Based Architecture for Time-to-Digital Converter. - Chia-Hua Wu; Shi-Yu Huang; Mason Chern; Yung-Fa Chou; Ding-Ming Kwai (ISVLSI, 2017)

Test strategies for the clock and power distribution networks in a multi-die IC. - Shi-Yu Huang (VLSI-DAT, 2017)

A Folded Locking Scheme for the Long-Range Delay Block in a Wide-Range DLL. - Yu-Chi Wei; Shi-Yu Huang (ISOCC, 2018)

A Cell-Based Fractional-N Phase-Locked Loop Compiler. - Cheng-En Lee; Shi-Yu Huang (SMACD, 2018)

Circuit and Methodology for Testing Small Delay Faults in the Clock Network. - Shaofu Yang; Zhi-Yuan Wen; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Improving scan chain diagnostic accuracy using multi-stage artificial neural networks. - Mason Chern; Shih-Wei Lee; Shi-Yu Huang; Yu Huang 005; Gaurav Veda; Kun-Han Hans Tsai; Wu-Tung Cheng (ASP-DAC, 2019)

The Ping-Pong Tunable Delay Line In A Super-Resilient Delay-Locked Loop. - Zheng-Hong Zhang; Wei Chu; Shi-Yu Huang (DAC, 2019)

Online Testing of Clock Delay Faults in a Clock Network. - Wei Chu; Shi-Yu Huang (ITC-Asia, 2019)

Overall Strategy for Online Clock System Checking Supporting Heterogeneous Integration. - Wei Chu; Shi-Yu Huang (ITC, 2019)

International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia. - Kuen-Jong Lee; Shi-Yu Huang; Huawei Li; Tomoo Inoue; Yervant Zorian (ITC, 2019)

A Cell-Based Wide-Frequency-Range DLL Supporting Fast Frequency Scaling. - Wei Chu; Shi-Yu Huang (NEWCAS, 2019)

Cloud-Based Online Ageing Monitoring for IoT Devices. - Guan-Hao Lian; Wei-yi Chen; Shi-Yu Huang (IEEE Access, 2019)

A Ping-Pong Methodology for Boosting the Resilience of Cell-Based Delay-Locked Loop. - Zheng-Hong Zhang; Wei Chu; Shi-Yu Huang (IEEE Access, 2019)

Overview of On-Chip Performance Monitors for Clock Signals. - Shi-Yu Huang (ATS, 2020)

Fault and Soft Error Tolerant Delay-Locked Loop. - Jun-Yu Yang; Shi-Yu Huang (ATS, 2020)

Duty-Cycle Correction For A Super-Wide Frequency Range from 10MHz to 1.2GHz. - Wei Chu; Wei-Hao Chen; Shi-Yu Huang (ICCD, 2020)

A Voting Phase Detector Design with Mitigated Process Variation. - Derek Lin; Jun-Yu Yang; Shi-Yu Huang (ISOCC, 2020)

Rapid PLL Monitoring By A Novel min-MAX Time-to-Digital Converter. - Wei-Hao Chen; Chu-Chun Hsu; Shi-Yu Huang (ITC, 2020)

Time-to-Digital Converter Compiler for On-Chip Instrumentation. - Chia-Hua Wu; Shi-Yu Huang; Yung-Fa Chou; Ding-Ming Kwai (IEEE Des. Test, 2020)

Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process. - Mason Chern; Shih-Wei Lee; Shi-Yu Huang; Yu Huang 005; Gaurav Veda; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Rigorous Test Flow for PLL to Identify Weak Devices. - Yi-Hsuan Lee; Shi-Yu Huang (ITC-Asia, 2021)

A Duty-Cycle Monitor Supporting A Wide Frequency Range of Clock Signal. - Chen-Lin Tsai; Wei-Hao Chen; Shi-Yu Huang (ITC-Asia, 2021)

Graph Neural Networks for Charged Particle Tracking on FPGAs. - Abdelrahman Elabd; Vesal Razavimaleki; Shi-Yu Huang; Javier M. Duarte; Markus Atkinson; Gage DeZoort; Peter Elmer; Jin-Xuan Hu; Shih-Chieh Hsu; Bo-Cheng Lai; Mark S. Neubauer; Isobel Ojalvo; et al. (CoRR, 2021)

Online Safety Checking for Delay Locked Loops via Embedded Phase Error Monitor. - Wei Chu; Shi-Yu Huang (IEEE Trans. Emerg. Top. Comput., 2021)

Just-Enough Strategy for Accurate Clock Jitter Measurement Using A Cyclic Time-to-Digital Converter. - Yung-Chuan Su; Shi-Yu Huang (ISOCC, 2022)

Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning. - Chen-Lin Tsai; Shi-Yu Huang (ITC, 2022)

On-Chip Jitter Learning for PLL. - Wei-Hao Chen; Shi-Yu Huang (IEEE Des. Test, 2022)

Graph Neural Networks for Charged Particle Tracking on FPGAs. - Abdelrahman Elabd; Vesal Razavimaleki; Shi-Yu Huang; Javier M. Duarte; Markus Atkinson; Gage DeZoort; Peter Elmer; Scott Hauck; Jin-Xuan Hu; Shih-Chieh Hsu; Bo-Cheng Lai; Mark S. Neubauer; et al. (Frontiers Big Data, 2022)

Process-Resilient Fault-Tolerant Delay-Locked Loop Using TMR With Dynamic Timing Correction. - Jun-Yu Yang; Shi-Yu Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Tiny Phase-Error Monitor for Fault and Soft-Error-Tolerant DLL to Support Graceful Degradation and Module-Level Testing. - Jun-Yu Yang; Shi-Yu Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs. - Shi-Yu Huang; Yun-Chen Yang; Yu-Ru Su; Bo-Cheng Lai; Javier M. Duarte; Scott Hauck; Shih-Chieh Hsu; Jin-Xuan Hu; Mark S. Neubauer (FPL, 2023)

Self-Sufficient Clock Jitter Measurement Methodology Using Dithering-Based Calibration. - Yi-Hsuan Lee; Wei-Hao Chen; Shi-Yu Huang (ITC-Asia, 2023)

Trustworthy Lifetime Prediction by Aging History Analysis and Multi-Level Stress Test. - Chen-Lin Tsai; Shi-Yu Huang (ITC-Asia, 2023)

Optimization of DCO Using Latch-Based Varactor Cells for a Cell-Based PLL. - Yi-Sheng Wang; Hsiang-Kai Teng; Shi-Yu Huang (MWSCAS, 2023)

Cell-Based Aging Sensor Using Built-In Speed Grading. - Ont-Derh Lin; Shi-Yu Huang (NorCAS, 2023)

Compiler of Reed-Solomon Codec for 400-Gb/s IEEE 802.3bs Standard. - Lin Liu; Lai Chi; Shi-Yu Huang; Ka-Yi Yeh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization. - Yung-Chuan Su; Shi-Yu Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Process-Adaptive Cell-Based Cyclic Time-to-Digital Converter Using One-Way Varactor Cells. - Yung-Chuan Su; Shi-Yu Huang (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Trojan Horse Detection for RISC-V Cores Using Cross-Auditing. - Wei-Po Huang; Shi-Yu Huang; Chi-Kang Chen; Siang-Cheng Huang (ATS, 2024)

Keynote 2 - Sustainability and the Outlook of Semiconductor Industry. - Cheng-Wen Wu; Shi-Yu Huang (ETS, 2024)

A Resilient All-Digital PLL Using Ping-Pong Delay Line. - Hsiang-Kai Teng; Shi-Yu Huang (ISOCC, 2024)

Small-Bridging-Fault-Aware Built-In-Self-Repair for Cycle-Based Interconnects in a Chiplet Design Using Adjusted Pulse-Vanishing Test. - Chi Lai; Shi-Yu Huang (ITC, 2024)

General Fault and Soft-Error Tolerant Phase-Locked Loop by Enhanced TMR using A Synchronization-before-Voting Scheme. - Shun-Hua Yang; Shi-Yu Huang (J. Electron. Test., 2024)

Instant Test and Repair for TSVs using Differential Signaling. - Ching-Yi Wen; Shi-Yu Huang (J. Electron. Test., 2024)

A Check-and-Balance Scheme in Multiphase Delay-Locked Loop. - Shu-Yu Chang; Shi-Yu Huang (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Low-Jitter Frequency Doubling Circuit Supporting Higher-Speed BISG and Aging Sensing in a Chiplet-Based Design Environment. - Ko-Hong Lin; Ont-Derh Lin; Shi-Yu Huang; Duo Sheng (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A Scalable Authentication Scheme for Detecting Unauthorized Dice in A Multi-Die IC. - Zheng-Hao Wang; Shi-Yu Huang; Chi-Kang Chen (SMACD, 2025)

Built-In Self-Repair of Small Delay Faults Occurring to TSVs in a 3D-DRAM Using an Enhanced Pulse-Vanishing Test. - Chen-Yu Huang; Shi-Yu Huang (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Connectivity-Agnostic Built-In Self-Repair of Interconnects in a Chiplet IC. - Chi Lai; Shi-Yu Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)