Library-Adaptively Integrated Data Path Synthesis for DSP Systems. - Jer-Min Jou; Shiann-Rong Kuang (ICCD, 1993)

Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization. - Jer-Min Jou; Ren-Der Chen; Shiann-Rong Kuang (ISCAS, 1994)

A New Pipelined Architecture for Fuzzy Color Correction. - Jer-Min Jou; Shiann-Rong Kuang; Yeu-Horng Shiau (ASP-DAC, 1999)

Design of a dynamic pipelined architecture for fuzzy color correction. - Jer-Min Jou; Shiann-Rong Kuang; Yeu-Horng Shiau; Ren-Der Chen (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Partitioning and Pipelined Scheduling of Embedded System Using Integer Linear Programming. - Shiann-Rong Kuang; Chin-Yang Chen; Ren-Zheng Liao (ICPADS (2), 2005)

Area-Efficient Signed Fixed-Width Multipliers with Low-Error Compensation Circuit. - Jiun-Ping Wang; Shiann-Rong Kuang (SiPS, 2007)

Design of power-efficient pipelined truncated multipliers with various output precision. - Shiann-Rong Kuang; Jiun-Ping Wang (IET Comput. Digit. Tech., 2007)

Modified Booth Multipliers With a Regular Partial Product Array. - Shiann-Rong Kuang; Jiun-Ping Wang; Cang-Yuan Guo (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Design of Power-Efficient Configurable Booth Multiplier. - Shiann-Rong Kuang; Jiun-Ping Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Variable-Latency Floating-Point Multipliers for Low-Power Applications. - Shiann-Rong Kuang; Jiun-Ping Wang; Hong-Yi Huang (IEEE Trans. Very Large Scale Integr. Syst., 2010)

High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications. - Jiun-Ping Wang; Shiann-Rong Kuang; Shish-Chang Liang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Multiple-mode floating-point multiply-add fused unit for trading accuracy with power consumption. - Kun-Yi Wu; Chih-Yuan Liang; Kee-Khuan Yu; Shiann-Rong Kuang (ICIS, 2013)

An exact method for estimating maximum errors of multi-mode floating-point iterative booth multiplier. - Kun-Yi Wu; Shiann-Rong Kuang; Kee-Khuan Yu (Int. J. Comput. Sci. Eng., 2013)

Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems. - Shiann-Rong Kuang; Jiun-Ping Wang; Kai-Cheng Chang; Huan-Wei Hsu (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications. - Shiann-Rong Kuang; Kun-Yi Wu; Kee-Khuan Yu (J. Signal Process. Syst., 2013)

Efficient architecture and hardware implementation of hybrid fuzzy-Kalman filter for workload prediction. - Shiann-Rong Kuang; Kun-Yi Wu; Bao-Chen Ke; Jia-Huei Yeh; Hao-Yi Jheng (Integr., 2014)

An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support. - Hsu-Kang Dow; Ching-Hua Huang; Chun-Hung Lai; Kai-Hsiang Tsao; Sheng-Chih Tseng; Kun-Yi Wu; Ting-Hsuan Wu; Ho-Chun Yang; Da-Jing Zhang-Jian; Yun-Nan Chang; Steve Haga; Shen-Fu Hsiao; et al. (VLSI-DAT, 2015)

An Efficient Radix-4 Scalable Architecture for Montgomery Modular Multiplication. - Shiann-Rong Kuang; Chih-Yuan Liang; Chun-Chi Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication. - Shiann-Rong Kuang; Kun-Yi Wu; Ren-Yao Lu (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Design and implementation of a low-cost guided image filter for underwater image enhancement. - Cheng-Hao Chang; I-Chang Huang; Mu-Fan Lin; Shiann-Rong Kuang (DSC, 2017)

Hardware Implementation of an Automatic Color Equalization Algorithm for Real-time Image Enhancement. - Xiang-Yu Chen; Yu-Hsiang Wang; Yao-Song Zhang; Yen-Jui Chen; Shiann-Rong Kuang (MCSoC, 2022)