CryptoScan: A Secured Scan Chain Architecture. - Debdeep Mukhopadhyay; Shibaji Banerjee; Dipanwita Roy Chowdhury; Bhargab B. Bhattacharya (Asian Test Symposium, 2005)

A programmable built-in self-test for embedded DRAMs. - Shibaji Banerjee; Dipanwita Roy Chowdhury; Bhargab B. Bhattacharya (MTDT, 2005)

Computer Aided Test (CAT) Tool for Mixed Signal SOCs. - Shibaji Banerjee; Debdeep Mukhopadhyay; Dipanwita Roy Chowdhury (VLSI Design, 2005)

Built-In Self-Test for Flash Memory Embedded in SoC. - Shibaji Banerjee; Dipanwita Roy Chowdhury (DELTA, 2006)

An integrated DFT solution for mixed-signal SOCs. - Shibaji Banerjee; Debdeep Mukhopadhyay; C. V. G. Rao; Dipanwita Roy Chowdhury (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

An Efficient Scan Tree Design for Compact Test Pattern Set. - Shibaji Banerjee; Dipanwita Roy Chowdhury; Bhargab B. Bhattacharya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization. - Shibaji Banerjee; Jimson Mathew; Dhiraj K. Pradhan; Saraju P. Mohanty; Maciej J. Ciesielski (VLSI Design, 2011)

A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. - Shibaji Banerjee; Jimson Mathew; Saraju P. Mohanty; Dhiraj K. Pradhan; Maciej J. Ciesielski (J. Low Power Electron., 2011)

A Routing-Aware ILS Design Technique. - Shibaji Banerjee; Jimson Mathew; Dhiraj K. Pradhan; Bhargab B. Bhattacharya; Saraju P. Mohanty (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity. - Jimson Mathew; Saraju P. Mohanty; Shibaji Banerjee; Dhiraj K. Pradhan; Abusaleh M. Jabir (Comput. Electr. Eng., 2013)

An Optimal Leakage-Aware Approach for Nano-CMOS Post-Physical-Optimization. - Shibaji Banerjee; Jimson Mathew (J. Low Power Electron., 2017)