An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop. - Lih-Yih Chiou; Shien-Chun Luo (ISCAS, 2007)

Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics. - Lih-Yih Chiou; Shien-Chun Luo (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing. - Shien-Chun Luo; Lih-Yih Chiou (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion. - Shien-Chun Luo; Chi-Ray Huang; Lih-Yih Chiou (ISCAS, 2012)

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. - Tay-Jyi Lin; Cheng-An Chien; Pei-Yao Chang; Ching-Wen Chen; Po-Hao Wang; Ting-Yu Shyu; Chien-Yung Chou; Shien-Chun Luo; Jiun-In Guo; Tien-Fu Chen; Gene C. H. Chuang; Yuan-Hua Chu; et al. (ISSCC, 2013)

An Adaptive Pulse-Triggered Flip-Flop for a High-Speed and Voltage-Scalable Standard Cell Library. - Shien-Chun Luo; Ching-Ji Huang; Yuan-Hua Chu (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

An ultra-low voltage hearing aid chip using variable-latency design technique. - Kuo-Chiang Chang; Shien-Chun Luo; Ching-Ji Huang; Chih-Wei Liu; Yuan-Hua Chu; Shyh-Jye Jou (ISCAS, 2014)

An ultra-low-power adaptive-body-bias control for subthreshold circuits. - Shien-Chun Luo; Chi-Ray Huang; Lih-Yih Chiou (VLSI-DAT, 2014)

Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells. - Shien-Chun Luo; Kuo-Chiang Chang; Ming-Pin Chen; Ching-Ji Huang; Yi-Fang Chiu; Po-Hsun Chen; Liang-Chia Cheng; Chih-Wei Liu; Yuan-Hua Chu (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A Wide-Range Level Shifter Using a Modified Wilson Current Mirror Hybrid Buffer. - Shien-Chun Luo; Ching-Ji Huang; Yuan-Hua Chu (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

MORAS: An energy-scalable system using adaptive voltage scaling. - Kuo-Chiang Chang; Shien-Chun Luo; Ching-Ji Huang; Jia-Hung Peng; Yuan-Hua Chu (VLSI-DAT, 2018)

Customization of a Deep Learning Accelerator. - Shien-Chun Luo (VLSI-DAT, 2019)

Configurable Deep Learning Accelerator with Bitwise-accurate Training and Verification. - Shien-Chun Luo; Kuo-Chiang Chang; Po-Wei Chen; Zhao-Hong Chen (VLSI-DAT, 2022)