XOR-Net: An Efficient Computation Pipeline for Binary Neural Network Inference on Edge Devices. - Shien Zhu; Luan H. K. Duong; Weichen Liu (ICPADS, 2020)

Cross-filter compression for CNN inference acceleration. - Fuyuan Lyu; Shien Zhu; Weichen Liu (CoRR, 2020)

Parallel Multipath Transmission for Burst Traffic Optimization in Point-to-Point NoCs. - Hui Chen 016; Zihao Zhang; Peng Chen 027; Shien Zhu; Weichen Liu (ACM Great Lakes Symposium on VLSI, 2021)

iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations. - Shien Zhu; Shiqing Li; Weichen Liu (ACM Great Lakes Symposium on VLSI, 2022)

EDLAB: A Benchmark for Edge Deep Learning Accelerators. - Hao Kong; Shuo Huai; Di Liu 002; Lei Zhang 072; Hui Chen 016; Shien Zhu; Shiqing Li; Weichen Liu; Manu Rastogi; Ravi Subramaniam; Madhu Athreya; M. Anthony Lewis (IEEE Des. Test, 2022)

Deep learning acceleration: from quantization to in-memory computing - Shien Zhu (2022)

TAB: Unified and Optimized Ternary, Binary, and Mixed-precision Neural Network Inference on the Edge. - Shien Zhu; Luan H. K. Duong; Weichen Liu (ACM Trans. Embed. Comput. Syst., 2022)

An Efficient Sparse LSTM Accelerator on Embedded FPGAs with Bandwidth-Oriented Pruning. - Shiqing Li; Shien Zhu; Xiangzhong Luo; Tao Luo 014; Weichen Liu (FPL, 2023)

iMAT: Energy-Efficient In-Memory Acceleration for Ternary Neural Networks With Sparse Dot Product. - Shien Zhu; Shuo Huai; Guochu Xiong; Weichen Liu (ISLPED, 2023)

FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks. - Shien Zhu; Luan H. K. Duong; Hui Chen 016; Di Liu 002; Weichen Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)