SOI-DRAM circuit technologies for low power high speed multigiga scale memories. - Shigehiro Kuge; Fukashi Morishita; Takahiro Tsuruda; Shigeki Tomishima; Masaki Tsukude; Tadato Yamagata; Kazutami Arimoto (IEEE J. Solid State Circuits, 1996)

A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme. - Masaki Tsukude; Shigehiro Kuge; Takeshi Fujino; Kazutami Arimoto (IEEE J. Solid State Circuits, 1997)

A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica. - Shigehiro Kuge; Tetsuo Kato; Kiyohiro Furutani; Shigeru Kikuda; Katsuyoshi Mitsui; Takeshi Hamamoto; Jun Setogawa; Kei Hamade; Yuichiro Komiya; Satoshi Kawasaki; Takashi Kono; Teruhiko Amano; et al. (IEEE J. Solid State Circuits, 2000)

An 8kB EEPROM-Emulation DataFLASH Module for Automotive MCU. - Shinji Kawai; Akira Hosogane; Shigehiro Kuge; Toshihiro Abe; Kohei Hashimoto; Tsukasa Oishi; Naoki Tsuji; Kiyohiko Sakakibara; Kenji Noguchi (ISSCC, 2008)