New current attenuator circuit in the current mode FFT LSI for OFDM. - Seong-Kweon Kim; Shigehito Saigusa; Suguru Kameda; Hiroyuki Nakase; Kazuo Tsubouchi (APCCAS (1), 2002)

A Fast fc Automatic Tuning Circuit with Wide Tuning Range for WCDMA Direct Conversion Receiver Systems. - Osamu Watanabe 003; Rui Ito; Shigehito Saigusa; Tadashi Arai; Tetsuro Itakura (IEICE Trans. Electron., 2007)

A Triple-Band WCDMA Direct Conversion Receiver IC with Reduced Number of Off-Chip Components and Digital Baseband Control Signals. - Osamu Watanabe 003; Rui Ito; Toshiya Mitomo; Shigehito Saigusa; Tadashi Arai; Takehiko Toyoda (IEICE Trans. Electron., 2008)

A single-chip RF tuner / OFDM demodulator for mobile digital TV application. - Tsuyoshi Sekine; Ryuichi Fujimoto; Yoshimitsu Takamatsu; Mitsumasa Nakamura; Takuya Hirakawa; Masato Ishii; Takaya Yasuda; Motohiko Hayashi; H. Itoh; Yoko Wada; Teruo Imayama; Tatsuro Oomoto; et al. (ESSCIRC, 2009)

A 1.9/2.4GHz dual band CMOS power amplifier with integrated AM-PM distortion canceller. - Kohei Onizuka; Hiroaki Ishihara; Masahiro Hosoya; Shigehito Saigusa; Osamu Watanabe 003; Shoji Otaka (CICC, 2011)

A Single-Chip RF Tuner/OFDM Demodulator for Mobile Digital TV Application. - Yoshimitsu Takamatsu; Ryuichi Fujimoto; Tsuyoshi Sekine; Takaya Yasuda; Mitsumasa Nakamura; Takuya Hirakawa; Masato Ishii; Motohiko Hayashi; Hiroya Ito; Yoko Wada; Teruo Imayama; Tatsuro Oomoto; et al. (IEICE Trans. Electron., 2011)

A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS. - Akihide Sai; Yuka Kobayashi; Shigehito Saigusa; Osamu Watanabe 003; Tetsuro Itakura (ISSCC, 2012)

A +30.5 dBm CMOS Doherty power amplifier with reliability enhancement technique. - Kohei Onizuka; Shigehito Saigusa; Shoji Otaka (VLSIC, 2012)

A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion. - Kohei Onizuka; Hiroaki Ishihara; Masahiro Hosoya; Shigehito Saigusa; Osamu Watanabe 003; Shoji Otaka (IEEE J. Solid State Circuits, 2012)

A 1.8GHz linear CMOS power amplifier with supply-path switching scheme for WCDMA/LTE applications. - Kohei Onizuka; Shigehito Saigusa; Shoji Otaka (ISSCC, 2013)

A 60 GHz Power Amplifier with 10 GHz 1-dB Bandwidth and 13.6% PAE in 65 nm CMOS. - Tong Wang 018; Toshiya Mitomo; Naoko Ono; Shigehito Saigusa; Osamu Watanabe 003 (IEICE Trans. Electron., 2013)

20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication. - Shigehito Saigusa; Toshiya Mitomo; Hidenori Okuni; Masahiro Hosoya; Akihide Sai; Shusuke Kawai; Tong Wang 018; Masanori Furuta; Kei Shiraishi; Koichiro Ban; Seiichiro Horikawa; Tomoya Tandai; et al. (ISSCC, 2014)

A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS. - Masanori Furuta; Hidenori Okuni; Masahiro Hosoya; Akihide Sai; Junya Matsuno; Shigehito Saigusa; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A 1024-QAM capable WLAN receiver with -56.3 dB image rejection ratio using self-calibration technique. - Shusuke Kawai; Toshiyuki Yamagishi; Yosuke Hagiwara; Shigehito Saigusa; Ichiro Seto; Shoji Otaka; Shuichi Ito (ISCAS, 2017)

An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer. - Shusuke Kawai; Hiromitsu Aoyama; Rui Ito; Yutaka Shimizu; Mitsuyuki Ashida; Asuka Maki; Tomohiko Takeuchi; Hiroyuki Kobayashi; Go Urakawa; Hiroaki Hoshino; Shigehito Saigusa; Kazushi Koyama; et al. (ISSCC, 2018)

A 1024-QAM Capable WLAN Receiver with -56.3dB Image Rejection Ratio Using Self-Calibration Technique. - Shusuke Kawai; Toshiyuki Yamagishi; Yosuke Hagiwara; Shigehito Saigusa; Ichiro Seto; Shoji Otaka; Shuichi Ito (IEICE Trans. Electron., 2018)

An 802.11ax 4 × 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer. - Shusuke Kawai; Rui Ito; Kengo Nakata; Yutaka Shimizu; Motoki Nagata; Tomohiko Takeuchi; Hiroyuki Kobayashi; Katsuyuki Ikeuchi; Takayuki Kato; Yosuke Hagiwara; Yuki Fujimura; Kentaro Yoshioka; et al. (IEEE J. Solid State Circuits, 2018)

A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Efficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os. - Kosuke Yanagidaira; Mario Sako; Yasuhiro Hirashima; Junya Matsuno; Yumi Higashi; Yutaka Shimizu; Akihiro Imamoto; Kazuaki Kawaguchi; Koji Tabata; Takeshi Nakano; Yusuke Ochi; Hiroaki Hoshino; et al. (ISSCC, 2025)