A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs. - Tsukasa Ooishi; Mikio Asakura; Shigeki Tomishima; Hideto Hidaka; Kazutami Arimoto; Kazuyasu Fujishima (IEEE J. Solid State Circuits, 1994)

An experimental 256-Mb DRAM with boosted sense-ground scheme. - Mikio Asakura; Tsukasa Ooishi; Masaki Tsukude; Shigeki Tomishima; Takahisa Eimori; Hideto Hidaka; Yoshikazu Ohno; Kazutani Arimoto; Kazuyasu Fujishima; Tadashi Nishimura; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1994)

Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs. - Tadato Yamagata; Shigeki Tomishima; Masaki Tsukude; Takahiro Tsuruda; Yasushi Hashizume; Kazutami Arimoto (IEEE J. Solid State Circuits, 1995)

SOI-DRAM circuit technologies for low power high speed multigiga scale memories. - Shigehiro Kuge; Fukashi Morishita; Takahiro Tsuruda; Shigeki Tomishima; Masaki Tsukude; Tadato Yamagata; Kazutami Arimoto (IEEE J. Solid State Circuits, 1996)

A 5.3-GB/s embedded SDRAM core with slight-boost scheme. - Akira Yamazaki; Tadato Yamagata; Makoto Hatakenaka; Atsushi Miyanishi; Isao Hayashi; Shigeki Tomishima; Atsuo Mangyo; Yoshio Yukinari; Takashi Tatsumi; Masashi Matsumura; Kazutami Arimoto; Michihiro Yamada (IEEE J. Solid State Circuits, 1999)

A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications. - Shigeki Tomishima; Takaharu Tsuji; Toshiaki Kawasaki; Masatoshi Ishikawa; Toshihiro Inokuchi; Hiroshi Kato; Hiroaki Tanizaki; Wataru Abe; Akinori Shibayama; Yoshifumi Fukushima; Mitsutaka Niiro; Masanao Maruta; et al. (IEEE J. Solid State Circuits, 2001)

A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test. - Shigeki Tomishima; Hiroaki Tanizaki; Mitsutaka Niiro; Masanao Maruta; Hideto Hidaka; T. Tada; Kenji Gamo (ITC, 2002)

0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability. - Hirohito Kikukawa; Shigeki Tomishima; Takaharu Tsuji; Toshiaki Kawasaki; Shouji Sakamoto; Masatoshi Ishikawa; Wataru Abe; Hiroaki Tanizaki; Hiroshi Kato; Toshitaka Uchikoba; Toshihiro Inokuchi; Manabu Senoh; et al. (IEEE J. Solid State Circuits, 2002)

13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology. - Fatih Hamzaoglu; Umut Arslan; Nabhendra Bisnik; Swaroop Ghosh; Manoj B. Lal; Nick Lindert; Mesut Meterelliyoz; Randy B. Osborne; Joodong Park; Shigeki Tomishima; Yih Wang; Kevin Zhang 001 (ISSCC, 2014)

A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. - Pei-Wen Luo; Chi-Kang Chen; Yu-Hui Sung; Wei Wu 024; Hsiu-Chuan Shih; Chia-Hsin Lee; Kuo-Hua Lee; Ming-Wei Li; Mei-Chiang Lung; Chun-Nan Lu; Yung-Fa Chou; Po-Lin Shih; et al. (VLSIC, 2015)

A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology. - Fatih Hamzaoglu; Umut Arslan; Nabhendra Bisnik; Swaroop Ghosh; Manoj B. Lal; Nick Lindert; Mesut Meterelliyoz; Randy B. Osborne; Joodong Park; Shigeki Tomishima; Yih Wang; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2015)

23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache. - Tah-Kang Joseph Ting; Gyh-Bin Wang; Ming-Hung Wang; Chun-Peng Wu; Chun-Kai Wang; Chun-Wei Lo; Li-Chin Tien; Der-Min Yuan; Yung-Ching Hsieh; Jenn-Shiang Lai; Wen-Pin Hsu; Chien-Chih Huang; et al. (ISSCC, 2017)

Enabling Homomorphically Encrypted Inference for Large DNN Models. - Guillermo Lloret-Talavera; Marc Jordà; Harald Servat; Fabian Boemer; Chetan Chauhan; Shigeki Tomishima; Nilesh N. Shah; Antonio J. Peña (IEEE Trans. Computers, 2022)