An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. - Takeshi Sakata; Masashi Horiguchi; Tomonori Sekiguchi; Shigeki Ueda; Hitoshi Tanaka; Eiji Yamasaki; Yoshinobu Nakagome; Masakazu Aoki; Toru Kaga; Makoto Ohkura; Ryo Nagai; Fumio Murai; et al. (IEEE J. Solid State Circuits, 1995)

Low-noise, high-speed data transmission using a ringing-canceling output buffer. - Tomonori Sekiguchi; Masashi Horiguchi; Takeshi Sakata; Yoshinobu Nakagome; Shigeki Ueda; Masakazu Aoki (IEEE J. Solid State Circuits, 1995)