An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time. - Takamoto Watanabe; Shigenori Yamauchi (IEEE J. Solid State Circuits, 2003)

A 0.0027-mm2 9.5-bit 50-MS/s all-digital A/D converter TAD in 65-nm digital CMOS. - Takamoto Watanabe; Shigenori Yamauchi; Tomohito Terasawa (ICECS, 2009)

All-Digital Quadrature Detection With TAD for Radio-Controlled Clocks/Watches. - Sumio Masuda; Takamoto Watanabe; Shigenori Yamauchi; Tomohito Terasawa (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

All-digital MEMS tuning-fork self-excited vibration control by phase-relation using TAD-based ADPLL. - Shigenori Yamauchi; Takamoto Watanabe (NEWCAS, 2015)