A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy. - Atsushi Ohba; Shigeki Ohbayashi; Toru Shiomi; Satoshi Takano; Kenji Anami; Hiroki Honda; Yoshiyuki Ishigaki; Masahiro Hatanaka; Shigeo Nagao; Shimpei Kayano (IEEE J. Solid State Circuits, 1991)