A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design. - Kenichi Imamiya; Jun-ichi Miyamoto; Shigeru Atsumi; Nobuaki Ohtsuka; Yukinori Muroya; Toshiyuki Sako; Masao Higashino; Yumiko Iyama; Seiichi Mori; Yoichi Ohshima; Hitoshi Araki; Yukio Kaneko; et al. (IEEE J. Solid State Circuits, 1990)

A 16-ns 1-Mb CMOS EPROM. - Masao Kuriyama; Shigeru Atsumi; Ken-ichi Imamiya; Yumiko Iyama; Naohiro Matsukawa; Hitoshi Araki; Kazuhito Narita; Kazunori Masuda; Sumio Tanaka (IEEE J. Solid State Circuits, 1990)

A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure. - Akira Umezawa; Shigeru Atsumi; Masao Kuriyama; Hironori Banba; Ken-ichi Imamiya; Kiyomi Naruke; Seiji Yamada; Etsushi Obi; Masamitsu Oshikiri; Tomoko Suzuki; Sumio Tanaka (IEEE J. Solid State Circuits, 1992)

A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation. - Shigeru Atsumi; Masao Kuriyama; Akira Umezawa; Hironori Banba; Kiyomi Naruke; Seiji Yamada; Yoichi Ohshima; Masamitsu Oshikiri; Yohei Hiura; Tomoko Yamane; Kuniyoshi Yoshikawa (IEEE J. Solid State Circuits, 1994)

A CMOS bandgap reference circuit with sub-1-V operation. - Hironori Banba; Hitoshi Shiga; Akira Umezawa; Takeshi Miyaba; Toru Tanzawa; Shigeru Atsumi; Koji Sakui (IEEE J. Solid State Circuits, 1999)

Optimization of word-line booster circuits for low-voltage flash memories. - Toru Tanzawa; Shigeru Atsumi (IEEE J. Solid State Circuits, 1999)

A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme. - Shigeru Atsumi; Akira Umezawa; Toru Tanzawa; Tadayuki Taura; Hitoshi Shiga; Yoshinori Takano; Takeshi Miyaba; Michiharu Matsui; Hiroshi Watanabe; Kazuaki Isobe; Shota Kitamura; Seiji Yamada; et al. (IEEE J. Solid State Circuits, 2000)

Design of a sense circuit for low-voltage flash memories. - Toru Tanzawa; Yoshinori Takano; Tadayuki Taura; Shigeru Atsumi (IEEE J. Solid State Circuits, 2000)

Wordline voltage generating system for low-power low-voltage flash memories. - Toru Tanzawa; Akira Umezawa; Masao Kuriyama; Tadayuki Taura; Hironori Banba; Takeshi Miyaba; Hitoshi Shiga; Yoshinori Takano; Shigeru Atsumi (IEEE J. Solid State Circuits, 2001)

High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories. - Toru Tanzawa; Yoshinori Takano; Kentaro Watanabe; Shigeru Atsumi (IEEE J. Solid State Circuits, 2002)

A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller. - Toru Tanzawa; Akira Umezawa; Tadayuki Taura; Hitoshi Shiga; Tokumasa Hara; Yoshinori Takano; Takeshi Miyaba; Naoya Tokiwa; Kentaro Watanabe; Hiroshi Watanabe; Kazunori Masuda; Kiyomi Naruke; et al. (IEEE J. Solid State Circuits, 2002)