A 300-MPOS video signal processor with a parallel architecture. - Toshihiro Minami; Ryota Kasai; Hironori Yamauchi; Yutaka Tashiro; Jun-ichi Takahashi; Shigeru Date (IEEE J. Solid State Circuits, 1991)

A 2-V, 2-GHz low-power direct digital frequency synthesizer chip-set for wireless communication. - Akihiro Yamagishi; Masayuki Ishikawa; Tsuneo Tsukahara; Shigeru Date (IEEE J. Solid State Circuits, 1998)