Hardware Organization of a Low Level Parallel Processor. - Shinji Tomita; Kiyoshi Shibayama; Shigeru Oyanagi; Hiroshi Hagiwara (IFIP Congress, 1977)

A Dynamically Microprogammable Computer with Low-Level Parallelism. - Hiroshi Hagiwara; Shinji Tomita; Shigeru Oyanagi; Kiyoshi Shibayama (IEEE Trans. Computers, 1980)

Network Performance of the Prodigy Parallel AI Machine. - Takashi Suzuoka; Noboru Tanabe; Sadao Nakamura; Sumikazu Fujita; Shigeru Oyanagi (Syst. Comput. Jpn., 1989)

Base-m n-cube: High Performance Interconnection Networks for Highly Parallel Computer PRODIGY. - Noboru Tanabe; Takashi Suzuoka; Sadao Nakamura; Yasushi Kawakura; Shigeru Oyanagi (ICPP (1), 1991)

Implementation of the prodigy parallel AI machine and performance evaluation of communication. - Noboru Tanabe; Sadao Nakamura; Takashi Suzuoka; Shigeru Oyanagi (Syst. Comput. Jpn., 1992)

Improving the Performance of Global Communication on a 3D torus network. - Yasushi Kawakura; Shigeru Oyanagi (ICPP (3), 1994)

Improving the performance of global communication on a three-dimensional torus network. - Yasushi Kawakura; Noboru Tanabe; Shigeru Oyanagi (Syst. Comput. Jpn., 1996)

Implementation and performance evaluation of dynamic scheduling for parallel decision tree generation. - Kazuto Kubota; Akihiko Nakase; Shigeru Oyanagi (IPDPS, 2001)

Mining WWW Access Sequence by Matrix Clustering. - Shigeru Oyanagi; Kazuto Kubota; Akihiko Nakase (WEBKDD, 2002)

Speculative Selection Routing in 2D Torus Network. - Tran Cong So; Shigeru Oyanagi; Katsuhiro Yamazaki (IEICE Trans. Inf. Syst., 2004)

ExMiner: An Efficient Algorithm for Mining Top-K Frequent Patterns. - Quang Tran Minh 001; Shigeru Oyanagi; Katsuhiro Yamazaki (ADMA, 2006)

Mining the K-Most Interesting Frequent Patterns Sequentially. - Quang Tran Minh 001; Shigeru Oyanagi; Katsuhiro Yamazaki (IDEAL, 2006)

Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding. - Anh Tuan Hoang; Katsuhiro Yamazaki; Shigeru Oyanagi (FCCM, 2008)

Three-stage pipeline implementation for SHA2 using data forwarding. - Anh Tuan Hoang; Katsuhiro Yamazaki; Shigeru Oyanagi (FPL, 2008)

Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance Rate. - Anh Tuan Hoang; Katsuhiro Yamazaki; Shigeru Oyanagi (IEICE Trans. Inf. Syst., 2009)

A Low Cost Single-Cycle Router Based on Virtual Output Queuing for On-chip Networks. - Son Truong Nguyen; Shigeru Oyanagi (DSD, 2010)

Control Independence Using Dual Renaming. - Lin Meng; Shigeru Oyanagi (ICNC, 2010)

The Design of On-the-Fly Virtual Channel Allocation for Low Cost High Performance On-Chip Routers. - Son Truong Nguyen; Shigeru Oyanagi (ICNC, 2010)

An Improvement of Router Throughput for On-Chip Networks Using On-the-fly Virtual Channel Allocation. - Son Truong Nguyen; Shigeru Oyanagi (ARCS, 2011)

An Input Buffer Architecture for On-chip Routers. - Chu Van Thiem; Shigeru Oyanagi (ICNC, 2011)

A Real-Time Burst Detection Method. - Ryohei Ebina; Kenji Nakamura; Shigeru Oyanagi (ICTAI, 2011)

Hybrid MPI-OpenMP Paradigm on SMP Clusters: MPEG-2 Encoder and N-Body Simulation - Truong Vinh Truong Duy; Katsuhiro Yamazaki; Kosai Ikegami; Shigeru Oyanagi (CoRR, 2012)

Performance Evaluation of Treecode Algorithm for N-Body Simulation Using GridRPC System - Truong Vinh Truong Duy; Katsuhiro Yamazaki; Shigeru Oyanagi (CoRR, 2012)

A Real-Time Burst Analysis Method. - Ryohei Ebina; Kenji Nakamura; Shigeru Oyanagi (Int. J. Artif. Intell. Tools, 2013)

The Development of Underwater-Drone equipped with 360-degree Panorama Camera in Opensource Hardware. - Lin Meng; Takuma Hirayama; Shigeru Oyanagi (IIKI, 2017)

Underwater-Drone With Panoramic Camera for Automatic Fish Recognition Based on Deep Learning. - Lin Meng; Takuma Hirayama; Shigeru Oyanagi (IEEE Access, 2018)