Optimization methods for lookup-table-based FPGAs using transduction method. - Shigeru Yamashita; Yahiko Kambayashi; Saburo Muroga (ASP-DAC, 1995)

A new method to express functional permissibilities for LUT based FPGAs and its applications. - Shigeru Yamashita; Hiroshi Sawada; Akira Nagoya (ICCAD, 1996)

Design of logic circuits with wired-logic utilizing transduction method. - Shigeru Yamashita; Yahiko Kambayashi; Saburo Muroga (Syst. Comput. Jpn., 1996)

Optimization methods for look-up table-type FPGAs based on permissible functions. - Shigeru Yamashita; Yahiko Kambayashi; Saburo Muroga (Syst. Comput. Jpn., 1996)

Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric Variables. - Hiroshi Sawada; Shigeru Yamashita; Akira Nagoya (Great Lakes Symposium on VLSI, 1997)

New Methods to Find Optimal Non-Disjoint Bi-Decompositions. - Shigeru Yamashita; Hiroshi Sawada; Akira Nagoya (ASP-DAC, 1998)

Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions. - Hiroshi Sawada; Shigeru Yamashita; Akira Nagoya (DATE, 1998)

An Integrated Approach for Synthesizing LUT Networks. - Shigeru Yamashita; Hiroshi Sawada; Akira Nagoya (Great Lakes Symposium on VLSI, 1999)

An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation. - Shigeru Yamashita; Hiroshi Sawada; Akira Nagoya (ASP-DAC, 2000)

SPFD: A new method to express functional flexibility. - Shigeru Yamashita; Hiroshi Sawada; Akira Nagoya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Transformation rules for designing CNOT-based quantum circuits. - Kazuo Iwama; Yahiko Kambayashi; Shigeru Yamashita (DAC, 2002)

Transformation Rules for CNOT-based Quantum Circuits and Their Applications. - Kazuo Iwama; Shigeru Yamashita (New Gener. Comput., 2003)

Efficient Algorithms for NMR Quantum Computers with Small Qubits. - Noboru Kunihiro; Shigeru Yamashita (New Gener. Comput., 2003)

SPFD-based one-to-many rewiring. - Katsunori Tanaka; Shigeru Yamashita; Yahiko Kambayashi (FPGA, 2004)

SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits. - Katsunori Tanaka; Shigeru Yamashita; Yahiko Kambayashi (ACM Great Lakes Symposium on VLSI, 2004)

Quantum Identification of Boolean Oracles. - Andris Ambainis; Kazuo Iwama; Akinori Kawachi; Hiroyuki Masuda; Raymond H. Putra; Shigeru Yamashita (STACS, 2004)

Event-oriented computing with reconfigurable platform. - Mitsuru Tomono; Masaki Nakanishi; Katsumasa Watanabe; Shigeru Yamashita (ASP-DAC, 2005)

Reconfigurable 1-Bit Processor Array with Reduced Wirng Area. - Nobuo Nakai; Masaki Nakanishi; Shigeru Yamashita; Katsumasa Watanabe (ERSA, 2005)

Quantum Sampling for Balanced Allocations. - Kazuo Iwama; Akinori Kawachi; Shigeru Yamashita (IEICE Trans. Inf. Syst., 2005)

SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits. - Katsunori Tanaka; Shigeru Yamashita; Yahiko Kambayashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A transduction-based framework to synthesize RSFQ circuits. - Shigeru Yamashita; Katsunori Tanaka; Hideyuki Takada; Koji Obata; Kazuyoshi Takagi (ASP-DAC, 2006)

A New Approach to Online FPGA Placement. - Mitsuru Tomono; Masaki Nakanishi; Shigeru Yamashita; Kazuo Nakajima; Katsumasa Watanabe (CISS, 2006)

Robust Quantum Algorithms with epsilon-Biased Oracles. - Tomoya Suzuki; Shigeru Yamashita; Masaki Nakanishi; Katsumasa Watanabe (COCOON, 2006)

(4, 1)-Quantum Random Access Coding Does Not Exist. - Masahito Hayashi; Kazuo Iwama; Harumichi Nishimura; Rudy Raymond; Shigeru Yamashita (ISIT, 2006)

An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs. - Mitsuru Tomono; Masaki Nakanishi; Shigeru Yamashita; Kazuo Nakajima; Katsumasa Watanabe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Quantum Biased Oracles. - Kazuo Iwama; Akinori Kawachi; Shigeru Yamashita (Inf. Media Technol., 2006)

Quantum lower bounds for the Goldreich-Levin problem. - Mark Adcock; Richard Cleve; Kazuo Iwama; Raymond H. Putra; Shigeru Yamashita (Inf. Process. Lett., 2006)

A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads. - Shinya Hiramoto; Masaki Nakanishi; Shigeru Yamashita; Yasuhiko Nakashima (ARC, 2007)

A practical framework to utilize quantum search. - Shigeru Yamashita; Masaki Nakanishi (IEEE Congress on Evolutionary Computation, 2007)

Unbounded-Error One-Way Classical and Quantum Communication Complexity. - Kazuo Iwama; Harumichi Nishimura; Rudy Raymond; Shigeru Yamashita (ICALP, 2007)

Unbounded-Error Classical and Quantum Communication Complexity. - Kazuo Iwama; Harumichi Nishimura; Rudy Raymond; Shigeru Yamashita (ISAAC, 2007)

Quantum Network Coding. - Masahito Hayashi; Kazuo Iwama; Harumichi Nishimura; Rudy Raymond Harry Putra; Shigeru Yamashita (STACS, 2007)

Robust Quantum Algorithms Computing OR with epsilon-Biased Oracles. - Tomoya Suzuki; Shigeru Yamashita; Masaki Nakanishi; Katsumasa Watanabe (IEICE Trans. Inf. Syst., 2007)

Improved algorithms for quantum identification of Boolean oracles. - Andris Ambainis; Kazuo Iwama; Akinori Kawachi; Rudy Raymond; Shigeru Yamashita (Theor. Comput. Sci., 2007)

An efficient verification of quantum circuits under a practical restriction. - Shigeru Yamashita; Shin-ichi Minato; D. Michael Miller (CIT, 2008)

Polynomial-Time Construction of Linear Network Coding. - Kazuo Iwama; Harumichi Nishimura; Mike Paterson; Rudy Raymond; Shigeru Yamashita (ICALP (1), 2008)

Quantum Query Complexity of Boolean Functions with Small On-Sets. - Andris Ambainis; Kazuo Iwama; Masaki Nakanishi; Harumichi Nishimura; Rudy Raymond; Seiichiro Tani; Shigeru Yamashita (ISAAC, 2008)

A Functional Unit with Small Variety of Highly Reliable Cells. - Kouki Suzuki; Takashi Nakada; Masaki Nakanishi; Shigeru Yamashita; Yasuhiko Nakashima (PRDC, 2008)

DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction. - Shigeru Yamashita; Shin-ichi Minato; D. Michael Miller (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Average/Worst-Case Gap of Quantum Query Complexities by On-Set Size - Andris Ambainis; Kazuo Iwama; Masaki Nakanishi; Harumichi Nishimura; Rudy Raymond; Seiichiro Tani; Shigeru Yamashita (CoRR, 2009)

Multi-Party Quantum Communication Complexity with Routed Messages. - Seiichiro Tani; Masaki Nakanishi; Shigeru Yamashita (IEICE Trans. Inf. Syst., 2009)

Synthesis of quantum circuits for d-level systems by using cosine-sine decomposition. - Yumi Nakajima; Yasuhito Kawano; Hiroshi Sekigawa; Masaki Nakanishi; Shigeru Yamashita; Yasuhiko Nakashima (Quantum Inf. Comput., 2009)

An Evaluation of "Face-to-Face" Group Activity on Blended-Learning in University Cooperation. - Yuki Mori; Shohei Shimada; Tetsuo Suemoto; Shigeru Yamashita; Shigeto Ozawa (ICCE, 2010)

Fast equivalence - checking for quantum circuits. - Shigeru Yamashita; Igor L. Markov (Quantum Inf. Comput., 2010)

An efficient algorithm for constructing a Sequence Binary Decision Diagram representing a set of reversed sequences. - Hiroshi Aoki; Shigeru Yamashita; Shin-ichi Minato (GrC, 2011)

Changing the Gate Order for Optimal LNN Conversion. - Atsushi Matsuo; Shigeru Yamashita (RC, 2011)

An efficient conversion of quantum circuits to a linear nearest neighbor architecture. - Yuichi Hirata; Masaki Nakanishi; Shigeru Yamashita; Yasuhiko Nakashima (Quantum Inf. Comput., 2011)

On error tolerance and Engineering Change with Partially Programmable Circuits. - Hratch Mangassarian; Hiroaki Yoshida; Andreas G. Veneris; Shigeru Yamashita; Masahiro Fujita (ASP-DAC, 2012)

An Optimization Problem for Topological Quantum Computation. - Shigeru Yamashita (Asian Test Symposium, 2012)

A redundant wire addition method for Patchable Accelerator. - Masayuki Wakizaka; Hiroaki Yoshida; Yuko Hara-Azumi; Shigeru Yamashita (ICECS, 2012)

Reconstructing Strings from Substrings with Quantum Queries. - Richard Cleve; Kazuo Iwama; François Le Gall; Harumichi Nishimura; Seiichiro Tani; Junichi Teruyama; Shigeru Yamashita (SWAT, 2012)

Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. - Marcos Villagra; Masaki Nakanishi; Shigeru Yamashita; Yasuhiko Nakashima (Electron. Colloquium Comput. Complex., 2012)

Quantum Walks on the Line with Phase Parameters. - Marcos Villagra; Masaki Nakanishi; Shigeru Yamashita; Yasuhiko Nakashima (IEICE Trans. Inf. Syst., 2012)

Synthesis of Semi-Classical Quantum Circuits. - Shigeru Yamashita; Shin-ichi Minato; D. Michael Miller (J. Multiple Valued Log. Soft Comput., 2012)

A clique-based approach to find binding and scheduling result in flow-based microfluidic biochips. - Trung Anh Dinh; Shigeru Yamashita; Tsung-Yi Ho; Yuko Hara-Azumi (ASP-DAC, 2013)

On the Error Resiliency of Combinational Logic Cells - Implications for Nano-based Digital Design. - P. Balasubramanian 001; Shigeru Yamashita (PRDC, 2013)

Selective Check of Data-Path for Effective Fault Tolerance. - Tanvir Ahmed 004; Jun Yao 001; Yuko Hara-Azumi; Shigeru Yamashita; Yasuhiko Nakashima (IEICE Trans. Inf. Syst., 2013)

Clique-Based Architectural Synthesis of Flow-Based Microfluidic Biochips. - Trung Anh Dinh; Shigeru Yamashita; Tsung-Yi Ho; Yuko Hara-Azumi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A network-flow-based optimal sample preparation algorithm for digital microfluidic biochips. - Trung Anh Dinh; Shigeru Yamashita; Tsung-Yi Ho (ASP-DAC, 2014)

A logic integrated optimal pin-count design for digital microfluidic biochips. - Trung Anh Dinh; Shigeru Yamashita; Tsung-Yi Ho (DATE, 2014)

Better-Than-DMR Techniques for Yield Improvement. - Shunichi Sanae; Yuko Hara-Azumi; Shigeru Yamashita; Yasuhiko Nakashima (FCCM, 2014)

2D Qubit Layout Optimization for Topological Quantum Computation. - Nurul Ain Binti Adnan; Shigeru Yamashita; Simon J. Devitt; Kae Nemoto (RC, 2014)

An Energy-Efficient Patchable Accelerator and Its Design Methods. - Hiroaki Yoshida; Masayuki Wakizaka; Shigeru Yamashita; Masahiro Fujita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Testing of digital microfluidic biochips with arbitrary layouts. - Trung Anh Dinh; Shigeru Yamashita; Tsung-Yi Ho; Krishnendu Chakrabarty (ETS, 2015)

A general testing method for digital microfluidic biochips under physical constraints. - Trung Anh Dinh; Shigeru Yamashita; Tsung-Yi Ho; Krishnendu Chakrabarty (ITC, 2015)

An Optimal Pin-Count Design With Logic Optimization for Digital Microfluidic Biochips. - Trung Anh Dinh; Shigeru Yamashita; Tsung-Yi Ho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

A systematic methodology for design and analysis of approximate array multipliers. - Takahiro Yamamoto; Ittetsu Taniguchi; Hiroyuki Tomiyama; Shigeru Yamashita; Yuko Hara-Azumi (APCCAS, 2016)

Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy. - Jason Helge Anderson; Yuko Hara-Azumi; Shigeru Yamashita (DATE, 2016)

A pre-optimization technique to generate initial reversible circuits with low quantum cost. - Nurul Ain Binti Adnan; Kouhei Kushida; Shigeru Yamashita (ISCAS, 2016)

Design of Microfluidic Biochips: Connecting Algorithms and Foundations of Chip Design to Biochemistry and the Life Sciences. - Tsung-Yi Ho; Shigeru Yamashita; Ansuman Banerjee; Sudip Roy 001 (VLSID, 2016)

Stochastic Number Generation with Few Inputs. - Ritsuko Muguruma; Shigeru Yamashita (VLSID, 2016)

ILP-based Synthesis for Sample Preparation Applications on Digital Microfluidic Biochips. - Abhimanyu Yadav; Trung Anh Dinh; Daiki Kitagawa; Shigeru Yamashita (VLSID, 2016)

Quantum Query Complexity of Almost All Functions with Fixed On-set Size. - Andris Ambainis; Kazuo Iwama; Masaki Nakanishi; Harumichi Nishimura; Rudy Raymond; Seiichiro Tani; Shigeru Yamashita (Comput. Complex., 2016)

Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders. - P. Balasubramanian 001; Shigeru Yamashita (CoRR, 2016)

A Full-Flexibility-Guaranteed Pin-Count Reduction Design for General-Purpose Digital Microfluidic Biochips. - Trung Anh Dinh; Shigeru Yamashita; Tsung-Yi Ho (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Reduction of Quantum Cost by Making Temporary Changes to the Function. - Nurul Ain Binti Adnan; Shigeru Yamashita; Alan Mishchenko (IEICE Trans. Inf. Syst., 2017)

Stochastic Number Generation with the Minimum Inputs. - Ritsuko Muguruma; Shigeru Yamashita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers. - Takahiro Yamamoto; Ittetsu Taniguchi; Hiroyuki Tomiyama; Shigeru Yamashita; Yuko Hara-Azumi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Microfluidic Biochips: Bridging Biochemistry with Computer Science and Engineering (NII Shonan Meeting 2017-1). - Shigeru Yamashita; Tsung-Yi Ho; Robert Wille; Krishnendu Chakrabarty (NII Shonan Meet. Rep., 2017)

Quantum Circuit Optimization by Changing the Gate Order for 2D Nearest Neighbor Architectures. - Wakaki Hattori; Shigeru Yamashita (RC, 2018)

Logical Qubit Layout Problem for ICM Representation. - Nurul Ain Binti Adnan; Shigeru Yamashita (J. Inf. Process., 2018)

Reducing the Overhead of Mapping Quantum Circuits to IBM Q System. - Atsushi Matsuo; Wakaki Hattori; Shigeru Yamashita (ISCAS, 2019)

Maximum Error-Aware Design of Approximate Array Multipliers. - Kenta Shirane; Takahiro Yamamoto; Ittetsu Taniguchi; Yuko Hara-Azumi; Shigeru Yamashita; Hiroyuki Tomiyama (ISOCC, 2019)

An Efficient Method for Quantum Circuit Placement Problem on a 2-D Grid. - Atsushi Matsuo; Shigeru Yamashita (RC, 2019)

Reactant Minimization for Multi-Target Sample Preparation on Digital Microfluidic Biochips Using Network Flow Models. - Kang-Yi Fan; Shigeru Yamashita; Juinn-Dar Huang (VLSI-DAT, 2019)

Reducing the Overhead of Stochastic Number Generators Without Increasing Error. - Yudai Sakamoto; Shigeru Yamashita (VLSID, 2019)

Compaction of Topological Quantum Circuits by Modularization. - Kota Asai; Shigeru Yamashita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Mapping a Quantum Circuit to 2D Nearest Neighbor Architecture by Changing the Gate Order. - Wakaki Hattori; Shigeru Yamashita (IEICE Trans. Inf. Syst., 2019)

Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments. - Chin-Heng Liu; Chia-Chun Lin; Yung-Chih Chen; Chia-Cheng Wu; Chun-Yao Wang; Shigeru Yamashita (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device-Based Biochips. - Ankur Gupta 002; Juinn-Dar Huang; Shigeru Yamashita; Sudip Roy 001 (ACM Trans. Design Autom. Electr. Syst., 2019)

Optimization of Fluid Loading on Programmable Microfluidic Devices for Bio-protocol Execution. - Satoru Maruyama; Debraj Kundu; Shigeru Yamashita; Sudip Roy 001 (ASP-DAC, 2020)

Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays. - Gautam Choudhary; Sandeep Pal; Debraj Kundu; Sukanta Bhattacharjee; Shigeru Yamashita; Bing Li 005; Ulf Schlichtmann; Sudip Roy 001 (DATE, 2020)

Reducing T-count When Decomposing Many MPMCT Gates Simultaneously. - Soma Esaki; Shigeru Yamashita (ISMVL, 2020)

Editorial for the special issue on disruptive computing technologies. - Yiran Chen 001; Deliang Fan; Yanzhi Wang; Shigeru Yamashita (CCF Trans. High Perform. Comput., 2020)

Efficient Methods to Generate Constant SNs with Considering Trade-Off between Error and Overhead and Its Evaluation. - Yudai Sakamoto; Shigeru Yamashita (IEICE Trans. Inf. Syst., 2020)

Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2-D Architecture and Its Application to Large-Scale Circuits. - Jingwen Ding; Shigeru Yamashita (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures. - Atsushi Matsuo; Wakaki Hattori; Shigeru Yamashita (ASP-DAC, 2021)

Minimization of Routing Area in MEDA Biochips. - Chiharu Shiro; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Shigeru Yamashita (BioCAS, 2021)

Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip. - Shuaijie Ying; Sudip Roy 001; Juinn-Dar Huang; Shigeru Yamashita (DSD, 2021)

Triple-Rail Stochastic Number and Its Applications. - Shoki Kawaminami; Shigeru Yamashita (ISOCC, 2021)

A Multiply Accumulator for Stochastic Numbers Without Scaling Errors. - Katsuhiro Ichikawa; Shigeru Yamashita (VLSID, 2021)

Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution. - Debraj Kundu; Jitendra Giri; Sataru Maruyama; Sudip Roy 001; Shigeru Yamashita (Integr., 2021)

Optimization of Quantum Boolean Circuits by Relative-Phase Toffoli Gates. - Shohei Kuroda; Shigeru Yamashita (RC, 2022)

Shape-Dependent Velocity Based Droplet Routing on MEDA Biochips. - Chiharu Shiro; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Shigeru Yamashita; Sudip Roy 001 (IEEE Access, 2022)

Approximating stochastic numbers to reduce latency. - Syoki Kawaminami; Yukino Watanabe; Shigeru Yamashita (it Inf. Technol., 2022)

Mixer-Based Washing Methods for Programmable Microfluidic Devices. - Yifang Bao; Shigeru Yamashita; Bing Li 005; Tsung-Yi Ho (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

An SMT-Solver-Based Synthesis of NNA-Compliant Quantum Circuits Consisting of CNOT, H and T Gates. - Kyohei Seino; Shigeru Yamashita (ASP-DAC, 2023)

Minimizing the Impact of Unbalanced Splitting Errors on DMFBs Without Any Overhead. - Yuji Wada; Shigeru Yamashita (DSD, 2023)

Multi-Droplet Routing based on a Shape-Dependent Velocity Model on MEDA Biochips. - Chiharu Shiro; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Shigeru Yamashita (ICEIC, 2023)

Optimizing LUT-Based Quantum Circuit Synthesis Using Relative Phase Boolean Operations. - David Clarino; Naoya Asada; Shigeru Yamashita (ICCAD, 2023)

Using S Gates and Relative Phase Toffoli Gates to Improve T-Count in Quantum Boolean Circuits. - David Clarino; Shohei Kuroda; Shigeru Yamashita (ISMVL, 2023)

A Deep Reinforcement Learning-based Routing Algorithm for Unknown Erroneous Cells in DMFBs. - Tomohisa Kawakami; Chiharu Shiro; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Shigeru Yamashita (NEWCAS, 2023)

A Fast Approach to Droplet Routing with Shape-Dependent Velocity on MEDA Biochips. - Kaito Mori; Chiharu Shiro; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Shigeru Yamashita (NEWCAS, 2023)

Transport-Free Placement of Mixers for Realizing Bioprotocol on Programmable Microfluidic Devices. - Masataka Hirai; Debraj Kundu; Shigeru Yamashita; Sudip Roy 001; Hiroyuki Tomiyama (VLSID, 2023)

An Efficient Method to Decompose and Map MPMCT Gates That Accounts for Qubit Placement. - Atsushi Matsuo; Wakaki Hattori; Shigeru Yamashita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Making General Dilution Graphs Robust to Unbalanced-Split Errors on Digital Microfluidic Biochips. - Ikuru Yoshida; Shigeru Yamashita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Preparing Fluid Samples Under Retention Time Constraints Using Flow-Based Microfluidic Biochips. - Debraj Kundu; Venkata Lavanya Sarvasiddi; Sukanta Bhattacharjee; Shigeru Yamashita; Sudip Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A SAT Approach to the Initial Mapping Problem in SWAP Gate Insertion for Commuting Gates. - Atsushi Matsuo; Shigeru Yamashita; Daniel J. Egger (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Enhancing VQE Convergence for Optimization Problems with Problem-Specific Parameterized Quantum Circuits. - Atsushi Matsuo; Yudai Suzuki; Ikko Hamamura; Shigeru Yamashita (IEICE Trans. Inf. Syst., 2023)

A Deep Reinforcement Learning Approach to Droplet Routing for Erroneous Digital Microfluidic Biochips. - Tomohisa Kawakami; Chiharu Shiro; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Shigeru Yamashita (Sensors, 2023)

Optimizing Decision Diagrams for Measurements of Quantum Circuits. - Ryosuke Matsuo; Rudy Raymond; Shigeru Yamashita; Shin-ichi Minato (ASPDAC, 2024)

Simultaneous Routing with Washing Droplets in MEDA Biochips. - Chiharu Shiro; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Shigeru Yamashita (ATAIT, 2024)

Multi-Resonance Mesh-Based Wavelength-Routed Optical Networks-on-Chip. - Zhidan Zheng; Liaoyuan Cheng; Kanta Arisawa; Qingyu Li; Alexandre Truppel; Shigeru Yamashita; Tsun-Ming Tseng; Ulf Schlichtmann (DAC, 2024)

An Efficient Cost Reduction Method By Reusing Intermediate Droplets in MEDA Biochips. - Kensuke Fukui; Shigeru Yamashita (ISOCC, 2024)

An Efficient Error Correction Method for DMFBs with Node Redundancy Considering Node Levels. - Suzuki Koki; Shigeru Yamashita (ISOCC, 2024)

Utilizing Don't-Cares to Minimize CNOTs in Synthesizing NNA Compliant Quantum Circuits. - David Clarino; Kyouhei Seino; Atsushi Matsuo; Shigeru Yamashita (QCE, 2024)

Optimization for Gaussian Elimination-Based NNA-Compliant Circuit Synthesis Method by Inserting CN OT Gates. - Zanhe Qi; Atsushi Matsuo; Shigeru Yamashita (QCE, 2024)

Efficient Realization of an SC Circuit with Feedback and Its Applications. - Yuto Arimura; Shigeru Yamashita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

Loading-Aware Mixing-Efficient Sample Preparation on Programmable Microfluidic Device. - Debraj Kundu; Tsun-Ming Tseng; Shigeru Yamashita; Ulf Schlichtmann (DATE, 2025)

Realizing 4-input Functions with the Minimum Toffoli Gate Count. - Shigeru Yamashita; Takashi Horiyama; Norihito Yasuda; Tatsuya Nakao (ISMVL, 2025)

A Decomposition Method for MCT Gates Considering T-depth of Each Qubit. - Zanhe Qi; Kouki Hirono; David Clarino; Shigeru Yamashita (ISVLSI, 2025)

Reducing T-Count in Quantum Circuits Using Alternate Forms of the Relative Phase Toffoli Gate. - David Clarino; Shohei Kuroda; Shigeru Yamashita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)

Leveraging Different Boolean Function Decompositions to Reduce T-Count in LUT-Based Quantum Circuit Synthesis. - David Clarino; Naoya Asada; Atsushi Matsuo; Shigeru Yamashita (IEICE Trans. Inf. Syst., 2025)