Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures. - Shigetaka Kumashiro; Ronald A. Rohrer; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Correlation method of circuit-performance and technology fluctuations for improved design reliability. - D. Miyawaki; Shizunori Matsumoto; Hans Jürgen Mattausch; S. Ooshiro; Masami Suetake; Mitiko Miura-Mattausch; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (ASP-DAC, 2001)

Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability. - Shizunori Matsumoto; Hans Jürgen Mattausch; S. Ooshiro; Y. Tatsumi; Mitiko Miura-Mattausch; Shigetaka Kumashiro; Terufumi Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (CICC, 2001)

Circuit Simulation Models for Coming MOSFET Generations. - Mitiko Miura-Mattausch; Hiroaki Ueno; Hans Jürgen Mattausch; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit design. - Kazuya Hisamitsu; Hiroaki Ueno; Masayasu Tanaka; Daisuke Kitamaru; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (ASP-DAC, 2003)

MOSFET harmonic distortion analysis up to the non-quasi-static frequency regime. - Youichi Takeda; Dondee Navarro; Shingo Chiba; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Tatsuya Ohguro; Takahiro Iizuka; Masahiko Taguchi; Shigetaka Kumashiro; Shunsuke Miyamoto (CICC, 2005)

1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation. - Shizunori Matsumoto; Hiroaki Ueno; Satoshi Hosokawa; Toshihiko Kitamura; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Tatsuya Ohguro; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (IEICE Trans. Electron., 2005)

A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential. - Dondee Navarro; Takeshi Mizoguchi; Masami Suetake; Kazuya Hisamitsu; Hiroaki Ueno; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (IEICE Trans. Electron., 2005)

Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress. - Kenta Yamada; Takashi Sato 001; Shuhei Amakawa; Noriaki Nakayama; Kazuya Masu; Shigetaka Kumashiro (IEICE Trans. Electron., 2008)

Non-quasi-static approach with surface-potential-based MOSFET model HiSIM for RF circuit simulations. - Tatsuya Ezaki; Dondee Navarro; Youichi Takeda; Norio Sadachika; Gaku Suzuki; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Tatsuya Ohguro; Takahiro Iizuka; Masahiko Taguchi; Shigetaka Kumashiro; Shunsuke Miyamoto (Math. Comput. Simul., 2008)

Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns. - Kenta Yamada; Toshiyuki Syo; Hisao Yoshimura; Masaru Ito; Tatsuya Kunikiyo; Toshiki Kanamoto; Shigetaka Kumashiro (IEICE Trans. Electron., 2010)

Accurate analysis of substrate sensitivity of active transistors in an analog circuit. - Satoshi Takaya; Yoji Bando; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Masaaki Souda; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (ISQED, 2011)

A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits. - Yoji Bando; Satoshi Takaya; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Masaaki Souda; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (IEICE Trans. Electron., 2011)

On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement. - Masaaki Souda; Yoji Bando; Satoshi Takaya; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (IEICE Trans. Electron., 2011)

HiSIM-RP: A reverse-profiling based 1st principles compact MOSFET model and its application to variability analysis of 90nm and 40nm CMOS. - Hironori Sakamoto; Shigetaka Kumashiro; Shigeo Sato; Naoki Wakita; Tohru Mogami (ISQED, 2012)

On-Chip In-Place Measurements of Vth and Signal/Substrate Response of Differential Pair Transistors. - Yoji Bando; Satoshi Takaya; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Masaaki Souda; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (IEICE Trans. Electron., 2012)

A predictable compact model for non-monotonous Vth-Pelgrom plot of long channel halo-implanted transistors. - Shigetaka Kumashiro (ISQED, 2013)

Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation. - Satoshi Takaya; Yoji Bando; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Masaaki Souda; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (IEICE Trans. Electron., 2013)

An Efficient and Accurate Time Step Control Method for Power Device Transient Simulation Utilizing Dominant Time Constant Approximation. - Shigetaka Kumashiro; Tatsuya Kamei; Akira Hiroki; Kazutoshi Kobayashi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Ultra Long-term Measurement Results of BTI-induced Aging Degradation on 7-nm Ring Oscillators. - Kazutoshi Kobayashi; Tomoharu Kishita; Hiroki Nakano; Jun Furuta; Mitsuhiko Igarashi; Shigetaka Kumashiro; Michitarou Yabuuchi; Hironori Sakamoto (IRPS, 2023)