Floating-point datapaths with online built-in self speed test. - Yasuhiko Hagihara; Shigeto Inui; Fuyuki Okamoto; Masato Nishida; Toshihiko Nakamura; Hachiro Yamada (IEEE J. Solid State Circuits, 1997)

Timing optimization by replacing flip-flops to latches. - Ko Yoshikawa; Yasuhiko Hagihara; Keisuke Kanamaru; Yuichi Nakamura 002; Shigeto Inui; Takeshi Yoshimura (ASP-DAC, 2004)

Domino Logic Synthesis System and its Applications. - Ko Yoshikawa; Shigeto Inui; Yasuhiko Hagihara; Yuichi Nakamura 002; Takeshi Yoshimura (J. Circuits Syst. Comput., 2006)