Channel-driven global routing with consistent placement (extended abstract). - Shigetoshi Nakatake; Yoji Kajitani (ICCAD, 1994)

Rectangle-packing-based module placement. - Hiroshi Murata; Kunihiro Fujiyoshi; Shigetoshi Nakatake; Yoji Kajitani (ICCAD, 1995)

Module placement on BSG-structure and IC layout applications. - Shigetoshi Nakatake; Kunihiro Fujiyoshi; Hiroshi Murata; Yoji Kajitani (ICCAD, 1996)

VLSI module placement based on rectangle-packing by the sequence-pair. - Hiroshi Murata; Kunihiro Fujiyoshi; Shigetoshi Nakatake; Yoji Kajitani (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules. - Shigetoshi Nakatake; Masahiro Furuya; Yoji Kajitani (ASP-DAC, 1998)

The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. - Shigetoshi Nakatake; Keishi Sakanushi; Yoji Kajitani; Masahiro Kawakita (ICCAD, 1998)

The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. - Keishi Sakanushi; Shigetoshi Nakatake; Yoji Kajitani (ICCAD, 1998)

Module packing based on the BSG-structure and IC layout applications. - Shigetoshi Nakatake; Kunihiro Fujiyoshi; Hiroshi Murata; Yoji Kajitani (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Self-reforming routing for stochastic search in VLSI interconnection layout. - Yukiko Kubo; Yasuhiro Takashima; Shigetoshi Nakatake; Yoji Kajitani (ASP-DAC, 2000)

Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. - Yoji Kajitani; Atsushi Takahashi 001; Kengo R. Azegami; Shigetoshi Nakatake (VLSI Design, 2000)

Consistent floorplanning with super hierarchical constraints. - Shigetoshi Nakatake; Yukiko Kubo; Yoji Kajitani (ISPD, 2001)

Chip size estimation based on wiring area. - Yukiko Kubo; Shigetoshi Nakatake; Yoji Kajitani; Masahiro Kawakita (APCCAS (2), 2002)

Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. - Yukiko Kubo; Shigetoshi Nakatake; Yoji Kajitani; Masahiro Kawakita (ASP-DAC/VLSI Design, 2002)

Consistent floorplanning with hierarchical superconstraints. - Shigetoshi Nakatake; Yukiko Kubo; Yoji Kajitani (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

An Incremental Wiring Algorithm for VLSI Layout Design. - Yukiko Kubo; Shigetoshi Nakatake; Yoji Kajitani; Masahiro Kawakita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Abstraction and optimization of consistent floorplanning with pillar block constraints. - Ning Fu; Shigetoshi Nakatake; Yasuhiro Takashima; Yoji Kajitani (ASP-DAC, 2004)

Multi-level placement with circuit schema based clustering in analog IC layouts. - Takashi Nojima; Xiaoke Zhu; Yasuhiro Takashima; Shigetoshi Nakatake; Yoji Kajitani (ASP-DAC, 2004)

A device-level placement with multi-directional convex clustering. - Takashi Nojima; Yasuhiro Takashima; Shigetoshi Nakatake; Yoji Kajitani (ACM Great Lakes Symposium on VLSI, 2004)

A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects. - Keiji Kida; Xiaoke Zhu; Changwen Zhuang; Yasuhiro Takashima; Shigetoshi Nakatake (ISCAS (4), 2004)

Sequence-Pair Based Compaction under Equi-Length Constraint. - Keiji Kida; Takehiko Matsuo; Tetsuya Tashiro; Shigetoshi Nakatake (APCCAS, 2006)

Multi-SP: A Representation with United Rectangles for Analog Placement and Routing. - Ning Fu; Mitsutoshi Mineshima; Shigetoshi Nakatake (ISVLSI, 2006)

Adaptive Porting of Analog IPs with Reusable Conservative Properties. - Takashi Nojima; Nobuto Ono; Shigetoshi Nakatake; Toru Fujimura; Koji Okazaki; Yoji Kajitani (ISVLSI, 2006)

Formulating the Empirical Strategies in Module Generation of Analog MOS Layout. - Tan Yan; Shigetoshi Nakatake; Takashi Nojima (ISVLSI, 2006)

The Oct-Touched Tile: A New Architecture for Shape-Based Routing. - Ning Fu; Shigetoshi Nakatake; Yasuhiro Takashima; Yoji Kajitani (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Structured Placement with Topological Regularity Evaluation. - Shigetoshi Nakatake (ASP-DAC, 2007)

Block placement to ensure channel routability. - Shigetoshi Nakatake; Zohreh Karimi; Taraneh Taghavi; Majid Sarrafzadeh (ACM Great Lakes Symposium on VLSI, 2007)

Constraint-free analog placement with topological symmetry structure. - Qing Dong 002; Shigetoshi Nakatake (ASP-DAC, 2008)

Transistor-level programmable MOS analog IC with body biasing. - Toru Fujimura; Shigetoshi Nakatake (ISCAS, 2008)

Fast Shape Optimization of Metallization Patterns for DMOS Based Driver. - Bo Yang 004; Shigetoshi Nakatake; Hiroshi Murata (ISQED, 2008)

A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion. - Bo Yang 004; Hiroshi Murata; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

STI stress aware placement optimization based on geometric programming. - Jing Li 072; Bo Yang 004; Xiaochuan Hu; Qing Dong 002; Shigetoshi Nakatake (ACM Great Lakes Symposium on VLSI, 2009)

Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming. - Qing Dong 002; Bo Yang 004; Jing Li 072; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Fast Shape Optimization of Metalization Patterns for Power-MOSFET Based Driver. - Bo Yang 004; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Structured Placement with Topological Regularity Evaluation. - Qing Dong 002; Shigetoshi Nakatake (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

D-A converter based variation analysis for analog layout design. - Bo Liu 031; Toru Fujimura; Bo Yang 004; Shigetoshi Nakatake (ASP-DAC, 2010)

Regularity-oriented analog placement with diffusion sharing and well island generation. - Shigetoshi Nakatake; Masahiro Kawakita; Takao Ito; Masahiro Kojima; Michiko Kojima; Kenji Izumi; Tadayuki Habasaki (ASP-DAC, 2010)

Structured analog circuit design and MOS transistor decomposition for high accuracy applications. - Bo Yang 004; Qing Dong 002; Jing Li 072; Shigetoshi Nakatake (ICCAD, 2010)

Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path. - Jing Li 072; Bo Yang 004; Qing Dong 002; Shigetoshi Nakatake (ISCAS, 2010)

Photomask Data Prioritization Based on VLSI Design Intent and Its Utilization for Mask Manufacturing. - Kokoro Kato; Masakazu Endo; Tadao Inoue; Shigetoshi Nakatake; Masaki Yamabe; Sunao Ishihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Regularity-Oriented Analog Placement with Conditional Design Rules. - Shigetoshi Nakatake; Masahiro Kawakita; Takao Ito; Masahiro Kojima; Michiko Kojima; Kenji Izumi; Tadayuki Habasaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Layout-aware variation evaluation of analog circuits and its validity on op-amp designs. - Kota Shinohara; Mihoko Hidaka; Jing Li 072; Qing Dong 002; Bo Yang 004; Shigetoshi Nakatake (ACM Great Lakes Symposium on VLSI, 2011)

Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis. - Bo Liu 031; Qing Dong 002; Bo Yang 004; Jing Li 072; Shigetoshi Nakatake (ISQED, 2011)

A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model. - Gong Chen 002; Bo Yang 004; Shigetoshi Nakatake; Zhangcai Huang; Yasuaki Inoue (ISCAS, 2012)

Transistor channel decomposition for structured analog layout, manufacturability and low-power applications. - Qing Dong 002; Bo Yang 004; Gong Chen 002; Jing Li 072; Shigetoshi Nakatake (ISQED, 2012)

CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects. - Yu Zhang; Bo Liu 031; Bo Yang 004; Jing Li 072; Shigetoshi Nakatake (ISQED, 2012)

Layout-Aware Variability Characterization of CMOS Current Sources. - Bo Liu 031; Bo Yang 004; Shigetoshi Nakatake (IEICE Trans. Electron., 2012)

A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm. - Gong Chen 002; Bo Yang 004; Yu Zhang; Qing Dong 002; Shigetoshi Nakatake (ACM Great Lakes Symposium on VLSI, 2013)

Practicality on placement given by optimality of packing. - Shigetoshi Nakatake (ISPD, 2013)

A comparator energy model considering shallow trench isolation stress by geometric programming. - Gong Chen 002; Yu Zhang; Bo Yang 004; Qing Dong 002; Shigetoshi Nakatake (ISQED, 2013)

Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects. - Yu Zhang; Gong Chen 002; Qing Dong 002; Mingyu Li; Shigetoshi Nakatake (VLSI-SoC, 2013)

Structured Analog Circuit and Layout Design with Transistor Array. - Bo Yang 004; Qing Dong 002; Jing Li 072; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming. - Yu Zhang; Gong Chen 002; Bo Yang 004; Jing Li 072; Qing Dong 002; Mingyu Li; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Subblock-level matching layout for analog block-pair and its manufacturability evaluation. - Takuya Hirata; Ryuta Nishino; Shigetoshi Nakatake; Masaya Shimoyama; Masashi Miyagawa; Koichi Tanno; Akihiro Yamada (ISCAS, 2015)

Low-Power and Low-Variability Programmable Delay Element and Its Application to Post-Silicon Skew Tuning. - Daijiro Murooka; Yu Zhang; Qing Dong 002; Shigetoshi Nakatake (ISVLSI, 2015)

Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC. - Gong Chen 002; Yu Zhang; Qing Dong 002; Mingyu Li; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Overview of the 2016 CAD contest at ICCAD. - Shih-Hsu Huang; Rung-Bin Lin; Myung-Chul Kim; Shigetoshi Nakatake (ICCAD, 2016)

Twin-row-style for MOS analog layout. - Bo Liu 031; Shigetoshi Nakatake; Bo Yang 004; Gong Chen 002 (ICECS, 2016)

Routability of twisted common-centroid capacitor array under signal coupling constraints. - Gong Chen 002; Bo Liu 031; Shigetoshi Nakatake; Bo Yang 004 (MWSCAS, 2016)

A multi-functional memory unit with PLA-based reconfigurable decoder. - Nobuyuki Yahiro; Bo Liu 031; Atsushi Nanri; Shigetoshi Nakatake; Yasuhiro Takashima; Gong Chen 002 (ReConFig, 2016)

A Sensor-Based Data Visualization System for Training Blood Pressure Measurement by Auscultatory Method. - Chooi-Ling Goh; Shigetoshi Nakatake (IEICE Trans. Inf. Syst., 2016)

Subblock-Level Matching Layout for Analog Block-Pair and Its Layout-Dependent Manufacturability Evaluation. - Takuya Hirata; Ryuta Nishino; Shigetoshi Nakatake; Masaya Shimoyama; Masashi Miyagawa; Ryoichi Miyauchi; Koichi Tanno; Akihiro Yamada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout. - Gong Chen 002; Toru Fujimura; Qing Dong 002; Shigetoshi Nakatake; Bo Yang 004 (ACM Trans. Design Autom. Electr. Syst., 2016)

Low Voltage Stochastic Flash ADC with Front-end of Inverter-based Comparative Unit. - Xuncheng Zou; Bo Liu 031; Shigetoshi Nakatake (ACM Great Lakes Symposium on VLSI, 2017)

Overview of the 2017 CAD contest at ICCAD: Invited paper. - Myung-Chul Kim; Shih-Hsu Huang; Rung-Bin Lin; Shigetoshi Nakatake (ICCAD, 2017)

Explicit layout pattern density controlling based on transistor-array-style. - Chao Geng; Bo Liu 031; Shigetoshi Nakatake (MWSCAS, 2017)

A Perceptron Circuit with DAC-Based Multiplier for Sensor Analog Front-Ends. - Yoritaka Ishiguchi; Daishi Isogai; Takuma Osawa; Shigetoshi Nakatake (NGCAS, 2017)

Analog Characterization Module with Data Converter-Coupled Signal Reconfiguration. - Daishi Isogai; Bo Liu 031; Yoritaka Ishiguchi; Shigetoshi Nakatake (NGCAS, 2017)

On-chip Impedance Evaluation with Auto-calibration based on Auto-balancing Bridge. - Takaaki Shirakawa; Ryosuke Sakai; Shigetoshi Nakatake (MWSCAS, 2018)

Hierarchical Floorplanning Based on Analog Structure Tree. - Chao Geng; Shigetoshi Nakatake (NGCAS, 2018)

Analog Retargeting Constraint Extraction Based on Fundamental Circuits and Layout Regularity. - Xuncheng Zou; Shigetoshi Nakatake (NGCAS, 2018)

Low Voltage CMOS Current Mode Reference Circuit without Operational Amplifiers. - Kenya Kondo; Koichi Tanno; Hiroki Tamura; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Analog perceptron circuit with DAC-based multiplier. - Yoritaka Ishiguchi; Daishi Isogai; Takuma Osawa; Shigetoshi Nakatake (Integr., 2018)

Routable and Matched Layout Styles for Analog Module Generation. - Bo Liu 031; Gong Chen 002; Bo Yang 004; Shigetoshi Nakatake (ACM Trans. Design Autom. Electr. Syst., 2018)

An Impedance Measurement of Intravesical Urine Volume Appropriate to Seated Posture. - Ryosuke Sakai; Shigetoshi Nakatake (APCCAS, 2019)

On-chip resistance configuration by subthreshold MOSFET-array for ultra weak current sensing. - Xinghuai Zhang; Shigetoshi Nakatake (APCCAS, 2019)

Density Optimization for Analog Layout Based on Transistor-Array. - Chao Geng; Bo Liu 031; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

A Low Voltage Stochastic Flash ADC without Comparator. - Xuncheng Zou; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

An Analog CMOS Implementation for Multi-layer Perceptron With ReLU Activation. - Chao Geng; Qingji Sun; Shigetoshi Nakatake (MOCAST, 2020)

A Fully Synthesizable, 0.3V, 10nW Rail-to-rail Dynamic Voltage Comparator. - Xuncheng Zou; Shigetoshi Nakatake (MWSCAS, 2020)

Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks. - Chao Geng; Qingji Sun; Shigetoshi Nakatake (Sensors, 2020)