A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's. - Shoichiro Kawashima; Toshihiko Mori; Ryuhei Sasagawa; Makoto Hamaminato; Shigetoshi Wakayama; Kazuo Sukegawa; Isao Fukushi (IEEE J. Solid State Circuits, 1998)

500-Mb/s nonprecharged data bus for high-speed DRAM's. - Miyoshi Saito; Junji Ogawa; Hirotaka Tamura; Shigetoshi Wakayama; Hisakatsu Araki; Tsz-Shing Cheung; Kohtaroh Gotoh; Tadao Aikawa; Takaaki Suzuki; Masao Taguchi; Takeshi Imamura (IEEE J. Solid State Circuits, 1998)