An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. - Shigeyoshi Watanabe; Yukihito Oowaki; Yasuo Itoh; Koji Sakui; Kenji Numata; Tsuneaki Fuse; Takayuki Kobayashi; Kenji Tsuchida; Masahiko Chiba; Takahiko Hara; Masako Ohta; Fumio Horiguchi; et al. (IEEE J. Solid State Circuits, 1989)

A 45-ns 16-Mbit DRAM with triple-well structure. - Syuso Fujii; Masaki Ogihara; Mitsuru Shimizu; Munehiro Yoshida; Kenji Numata; Takahiko Hara; Shigeyoshi Watanabe; Shizuo Sawada; Tomohisa Mizuno; Junpei Kumagai; Susumu Yoshikawa; Sejii Kaki; et al. (IEEE J. Solid State Circuits, 1989)

The stabilized reference-line (SRL) technique for scaled DRAMs. - Kenji Tsuchida; Yukihito Oowaki; Masako Ohta; Daisaburo Takashima; Shigeyoshi Watanabe; Kazuya Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1990)

A 33-ns 64-Mb DRAM. - Yukihito Oowaki; Kenji Tsuchida; Yohji Watanabe; Daisaburo Takashima; Masako Ohta; Hiroaki Nakano; Shigeyoshi Watanabe; Akihiro Nitayama; Fumio Horiguchi; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1991)

Word-line architecture for highly reliable 64-Mb DRAM. - Daisaburo Takashima; Yukihito Oowaki; Ryu Ogiwara; Yohji Watanabe; Kenji Tsuchida; Masako Ohta; Hiroaki Nakano; Shigeyoshi Watanabe; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1992)

BiCMOS circuit technology for high-speed DRAMs. - Shigeyoshi Watanabe; Koji Sakui; Tsuneaki Fuse; Takahiko Hara; Seiichi Aritome; Katsuhiko Hieda (IEEE J. Solid State Circuits, 1993)

Low-power on-chip supply voltage conversion scheme for ultrahigh-density DRAMs. - Daisaburo Takashima; Shigeyoshi Watanabe; Tsuneaki Fuse; Kazumasa Sunouchi; Takahiko Hara (IEEE J. Solid State Circuits, 1993)

An experimental DRAM with a NAND-structured cell. - Takehiro Hasegawa; Daisaburo Takashima; Ryu Ogiwara; Masako Ohta; Shinichiro Shiratake; Takeshi Hamamoto; Takashi Yamada; Masami Aoki; Shigeru Ishibashi; Yukihito Oowaki; Shigeyoshi Watanabe; Fujio Masuoka (IEEE J. Solid State Circuits, 1993)

Offset compensating bit-line sensing scheme for high density DRAM's. - Yohji Watanabe; Nobuo Nakamura; Shigeyoshi Watanabe (IEEE J. Solid State Circuits, 1994)

Open/folded bit-line arrangement for ultra-high-density DRAM's. - Daisaburo Takashima; Shigeyoshi Watanabe; Hiroaki Nakano; Yukihito Oowaki; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1994)

Standby/active mode logic for sub-1-V operating ULSI memory. - Daisaburo Takashima; Shigeyoshi Watanabe; Hiroalu Nakano; Yukihito Oowaki; Kazunori Ohuchi; Hiroyuki Tango (IEEE J. Solid State Circuits, 1994)

Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's. - Daisaburo Takashima; Yukihito Oowaki; Shigeyoshi Watanabe; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1998)

Individual Level Analysis Using Decision Making Features in Multiagent Based Simulation. - Tomomi Takashina; Kazuhide Tanaka; Shigeyoshi Watanabe (PRIMA, 2002)

Intelligent control in dynamic system. - Ariuna Damba; Shigeyoshi Watanabe (RAM, 2004)

MASSE: environment supporting for simulation and analysis of multiagent systems. - Tomomi Takashina; Zhenbo Bi; Ariuna Damba; Guilan Zhi; Kazuhide Tanaka; Hiroki Sayama; Shigeyoshi Watanabe (CTS, 2005)

Culture & Motivation: Establishing an International Storytelling Forum. - Zuoliang Chen; Shigeyoshi Watanabe (CELDA, 2005)

Policy Control in Multiagent System. - Ariuna Damba; Shigeyoshi Watanabe (Computational Intelligence, 2005)

A Fuzzy Model for Bidding Behavior of Participants in Electricity Markets. - Guilan Zhi; Shigeyoshi Watanabe (ICICIC (2), 2006)

Design of a 128-mb SOI DRAM using the floating body cell (FBC). - Takashi Ohsawa; Katsuyuki Fujita; Kosuke Hatsuda; Tomoki Higashi; Tomoaki Shino; Yoshihiro Minami; Hiroomi Nakajima; Mutsuo Morikado; Kazumi Inoh; Takeshi Hamamoto; Shigeyoshi Watanabe; Shuso Fujii; et al. (IEEE J. Solid State Circuits, 2006)

Comparison of discriminatory pricing and uniform pricing rules in electricity markets using an agent model with risk consideration. - Guilan Zhi; Shigeyoshi Watanabe (IEEE Congress on Evolutionary Computation, 2007)

A Case Study of Applying SNA to Analyze CSCL Social Network. - Zuoliang Chen; Shigeyoshi Watanabe (ICALT, 2007)

A Quantitative Method for Comparing Multi-Agent-Based Simulations in Feature Space. - Ryota Arai; Shigeyoshi Watanabe (MABS, 2008)

Subtractive Color Process for Lossless Compression of Non-photographed Images. - Yasuyuki Miura; Masato Suzuki; Ryo Morikawa; Shigeyoshi Watanabe (IPCV, 2010)

Adaptive routing algorithms and implementation for interconnection network TESH for parallel processing. - Yasuyuki Miura; Masahiro Kaneko; Shigeyoshi Watanabe (LCN, 2010)

Foreword. - Shigeyoshi Watanabe (IEICE Trans. Electron., 2010)

An Adaptive Routing of the 2-D Torus Network Based on Turn Model. - Yasuyuki Miura; Kazuya Matoyama; Kentaro Shimozono; Shigeyoshi Watanabe (CANDAR, 2013)

Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs. - Manabu Kobayashi; Hiroshi Ninomiya; Shigeyoshi Watanabe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Reduced Reconfigurable Logic Circuit Design Based on Double Gate CNTFETs Using Ambipolar Binary Decision Diagram. - Hiroshi Ninomiya; Manabu Kobayashi; Shigeyoshi Watanabe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Analysis of emission right prices in greenhouse gas emission trading via agent-based model. - Tomohiro Nakada; Keiki Takadama; Shigeyoshi Watanabe (Multiagent Grid Syst., 2013)

The Proposal of Partial Sharing for Link-Sharing Method of Buffer in NoC Router. - Naohisa Fukase; Yasuyuki Miura; Shigeyoshi Watanabe; M. M. Hafizur Rahman (CANDAR, 2014)

Reconfigurable Dynamic Logic Circuit Generating t-Term Boolean Functions Based on Double-Gate CNTFETs. - Manabu Kobayashi; Hiroshi Ninomiya; Yasuyuki Miura; Shigeyoshi Watanabe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Reconfigurable Circuit Design Based on Arithmetic Logic Unit Using Double-Gate CNTFETs. - Hiroshi Ninomiya; Manabu Kobayashi; Yasuyuki Miura; Shigeyoshi Watanabe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

An Adaptive Routing Algorithm of 2-D Torus Network Based on Turn Model: The Communication Performance. - Yasuyuki Miura; Kentaro Shimozono; Naohisa Fukase; Shigeyoshi Watanabe; Kazuya Matoyama (Int. J. Netw. Comput., 2015)

The performance evaluation of 3D torus using link-sharing method in NoC router. - Naohisa Fukase; Yasuyuki Miura; Shigeyoshi Watanabe; M. M. Hafizur Rahman (ICCE-TW, 2016)

The Performance Evaluation of a 3D Torus Network Using Partial Link-Sharing Method in NoC Router Buffer. - Naohisa Fukase; Yasuyuki Miura; Shigeyoshi Watanabe; M. M. Hafizur Rahman (IEICE Trans. Inf. Syst., 2017)