Synthesis of false loop free circuits. - Shih-Hsu Huang; Ta-Yung Liu; Yu-Chin Hsu; Yen-Jen Oyang (ASP-DAC, 1995)

A new approach to schedule operations across nested-ifs and nested-loops. - Shih-Hsu Huang; Cheng-Tsung Hwang; Yu-Chin Hsu; Yen-Jen Oyang (Microprocess. Microprogramming, 1995)

A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits. - Shih-Hsu Huang; Yu-Chin Hsu; Yen-Jen Oyang (Microprocess. Microprogramming, 1995)

A Reliable Clock Tree Design Methodology for ASIC Designs. - Mely Chen Chi; Shih-Hsu Huang (ISQED, 2000)

A High Speed VLSI Fuzzy Logic Controller With Pipeline Architecture. - Shih-Hsu Huang; Jian-Yuan Lai (FUZZ-IEEE, 2001)

An effective low power design methodology based on interconnect prediction. - Shih-Hsu Huang (SLIP, 2001)

A timing driven approach for crosstalk minimization in gridded channel routing. - Shih-Hsu Huang; Yi-Siang Hsu (APCCAS (1), 2002)

Automatic synthesis of fuzzy systems based on trapezoid-shaped membership functions. - Shih-Hsu Huang; Wen-Hon Peng; Jian-Yuan Lai (APCCAS (2), 2002)

An effective floorplan-based power distribution network design methodology under reliability constraints. - Shih-Hsu Huang; Chu-Liao Wang (ISCAS (1), 2002)

Clock Period Minimization of Non-Zero Clock Skew Circuits. - Shih-Hsu Huang; Yow-Tyng Nieh (ICCAD, 2003)

A Timing Driven Crosstalk Optimizer for Gridded Channel Routing. - Shih-Hsu Huang; Yi-Siang Hsu; Chiu-Cheng Lin (IEICE Trans. Inf. Syst., 2004)

Race-condition-aware clock skew scheduling. - Shih-Hsu Huang; Yow-Tyng Nieh; Feng-Pin Lu (DAC, 2005)

Minimizing peak current via opposite-phase clock tree. - Yow-Tyng Nieh; Shih-Hsu Huang; Sheng-Yu Hsu (DAC, 2005)

A formal approach to the slack driven scheduling problem in high-level synthesis. - Shih-Hsu Huang; Chun-Hua Cheng (ISCAS (6), 2005)

VLSI implementation of type-2 fuzzy inference processor. - Shih-Hsu Huang; Yi-Rung Chen (ISCAS (4), 2005)

Floorplanning with clock tree estimation. - Chih-Hung Lee; Chin-Hung Su; Shih-Hsu Huang; Chih-Yuan Lin; Tsai-Ming Hsieh (ISCAS (6), 2005)

Three-dimension scheduling under multi-cycle interconnect communications. - Shih-Hsu Huang; Chung-Hsin Chiang; Chun-Hua Cheng (IEICE Electron. Express, 2005)

A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities. - Shih-Hsu Huang; Jian-Yuan Lai (IEICE Trans. Inf. Syst., 2005)

High-Speed VLSI Fuzzy Inference Processor for Trapezoid-Shaped Membership Functions. - Shih-Hsu Huang; Jian-Yuan Lai (J. Inf. Sci. Eng., 2005)

Operation Scheduling for False Loop Free Circuits. - Shih-Hsu Huang; Chun-Hua Cheng (APCCAS, 2006)

Peak Power Minimization through Power Management Scheduling. - Shih-Hsu Huang; Chun-Hua Cheng; Chung-Hsin Chiang; Chia-Ming Chang 002 (APCCAS, 2006)

Fast multi-domain clock skew scheduling for peak current reduction. - Shih-Hsu Huang; Chia-Ming Chang 002; Yow-Tyng Nieh (ASP-DAC, 2006)

Register binding for clock period minimization. - Shih-Hsu Huang; Chun-Hua Cheng; Yow-Tyng Nieh; Wei-Chieh Yu (DAC, 2006)

State re-encoding for peak current minimization. - Shih-Hsu Huang; Chia-Ming Chang 002; Yow-Tyng Nieh (ICCAD, 2006)

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. - Shih-Hsu Huang; Chun-Hua Cheng; Chung-Hsin Chiang; Chia-Ming Chang 002 (JCIS, 2006)

High-Speed Fuzzy Inference Processor Using Active Rules Identification. - Shih-Hsu Huang; Shi-Zhi Liu; Yi-Rung Chen; Jian-Yuan Lai (JCIS, 2006)

An ILP Approach to the Slack Driven Scheduling Problem. - Shih-Hsu Huang; Chun-Hua Cheng (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Synthesis of nonzero clock skew circuits. - Shih-Hsu Huang; Yow-Tyng Nieh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Clock Period Minimization with Minimum Delay Insertion. - Shih-Hsu Huang; Chun-Hua Cheng; Chia-Ming Chang 002; Yow-Tyng Nieh (DAC, 2007)

A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs. - Shih-Hsu Huang; Chu-Liao Wang; Man-Lin Huang (EUC, 2007)

Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential. - Wei-Ting Yen; Shih-Hsu Huang; Chun-Hua Cheng (EUC Workshops, 2007)

Operation scheduling for the synthesis of false loop free circuits. - Shih-Hsu Huang; Chun-Hua Cheng (IEICE Electron. Express, 2007)

Opposite-Phase Clock Tree for Peak Current Reduction. - Yow-Tyng Nieh; Shih-Hsu Huang; Sheng-Yu Hsu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains. - Shih-Hsu Huang; Chia-Ming Chang 002; Yow-Tyng Nieh (J. Inf. Sci. Eng., 2007)

Clock skew scheduling with race conditions considered. - Shih-Hsu Huang; Yow-Tyng Nieh (ACM Trans. Design Autom. Electr. Syst., 2007)

Type-matching clock tree for zero skew clock gating. - Chia-Ming Chang 002; Shih-Hsu Huang; Yuan-Kai Ho; Jia-Zong Lin; Hsin-Po Wang 002; Yu-Sheng Lu (DAC, 2008)

Module binding for low power clock gating. - Chun-Hua Cheng; Shih-Hsu Huang; Wen-Pin Tu (IEICE Electron. Express, 2008)

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. - Shih-Hsu Huang; Chun-Hua Cheng (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Power-Management Scheduling for Peak Power Minimization. - Shih-Hsu Huang; Chun-Hua Cheng (J. Inf. Sci. Eng., 2008)

Timing driven power gating in high-level synthesis. - Shih-Hsu Huang; Chun-Hua Cheng (ASP-DAC, 2009)

Surge Current Minimization in High-level Synthesis. - Jheng-Fu Yeh; Chun-Hua Cheng; Shih-Hsu Huang (ISCAS, 2009)

An ILP approach to surge current minimization in high-level synthesis. - Shih-Hsu Huang; Jheng-Fu Yeh; Chun-Hua Cheng (IEICE Electron. Express, 2009)

Synthesis of Anti-Aging Gated Clock Designs. - Shih-Hsu Huang; Chun-Hua Cheng; Song-Bin Pan (J. Inf. Sci. Eng., 2009)

Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization. - Shih-Hsu Huang; Chun-Hua Cheng; Da-Chen Tzeng (J. Inf. Sci. Eng., 2009)

Minimum-Period Register Binding. - Shih-Hsu Huang; Chun-Hua Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Opposite-phase register switching for peak current minimization. - Shih-Hsu Huang; Chia-Ming Chang 002; Yow-Tyng Nieh (ACM Trans. Design Autom. Electr. Syst., 2009)

Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating. - Shih-Hsu Huang; Chia-Ming Chang 002; Wen-Pin Tu; Song-Bin Pan (ASP-DAC, 2010)

Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization. - Shih-Hsu Huang; Chun-Hua Cheng (J. Inf. Sci. Eng., 2010)

Teaching three-dimensional system-in-package design automation in a semester course. - Shih-Hsu Huang; Wen-Pin Tu; Hua-Hsin Yeh; Chun-Hua Cheng (MSE, 2011)

TSV sharing through multiplexing for TSV count minimization in high-level synthesis. - Wen-Pin Tu; Yen-Hsin Lee; Shih-Hsu Huang (SoCC, 2011)

Minimum Inserted Buffers for Clock Period Minimization. - Shih-Hsu Huang; Guan-Yu Jhuo; Wei-Lun Huang (J. Inf. Sci. Eng., 2011)

Accurate TSV Number Minimization in High-Level Synthesis. - Chih-Hung Lee; Shih-Hsu Huang; Chun-Hua Cheng (J. Inf. Sci. Eng., 2011)

Simultaneous wafer bonding type selection and layer assignment for TSV count minimization. - Chun-Hua Cheng; Wei-Shuo Tzeng; Shih-Hsu Huang (APCCAS, 2012)

Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits. - Wen-Pin Tu; Shih-Hsu Huang; Chun-Hua Cheng (ASP-DAC, 2012)

NBTI-aware dual threshold voltage assignment for leakage power reduction. - Wen-Pin Tu; Shih-Wei Wu; Shih-Hsu Huang; Mely Chen Chi (ISCAS, 2012)

A formal approach to slack-driven high-level synthesis. - Hua-Hsin Yeh; Shih-Hsu Huang; Chun-Hua Cheng (ISCAS, 2012)

High-Level Synthesis for Minimum-Area Low-Power Clock Gating. - Shih-Hsu Huang; Wen-Pin Tu; Bing-Hung Li (J. Inf. Sci. Eng., 2012)

Co-synthesis of data paths and clock control paths for minimum-period clock gating. - Wen-Pin Tu; Shih-Hsu Huang; Chun-Hua Cheng (DATE, 2013)

Low-power timing closure methodology for ultra-low voltage designs. - Wen-Pin Tu; Chung-Han Chou; Shih-Hsu Huang; Shih-Chieh Chang; Yow-Tyng Nieh; Chien-Yung Chou (ICCAD, 2013)

Low-power anti-aging zero skew clock gating. - Shih-Hsu Huang; Wen-Pin Tu; Chia-Ming Chang 002; Song-Bin Pan (ACM Trans. Design Autom. Electr. Syst., 2013)

Self-adjusting mechanism to dynamically suppress the effect of PVT variations on clock skew. - Tsung-Tang Lin; Wen-Pin Tu; Shih-Hsu Huang (APCCAS, 2014)

Abstract bus interface unit for ESL design from TLM 2.0 communications to the real bus protocol. - Hua-Hsin Yeh; Wen-Pin Tu; Jian-Zhi Shen; Tung-Hua Yen; Shih-Hsu Huang (APCCAS, 2014)

Live demonstration: A low-power high-level synthesis system. - Hua-Hsin Yeh; Chun-Hua Cheng; Shih-Hsu Huang (APCCAS, 2014)

Leakage-power-aware clock period minimization. - Hua-Hsin Yeh; Shih-Hsu Huang; Yow-Tyng Nieh (DATE, 2014)

Temperature-Aware Layer Assignment for Three-Dimensional Integrated Circuits. - Shih-Hsu Huang; Hua-Hsin Yeh (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Overview of the 2015 CAD Contest at ICCAD. - Natarajan Viswanathan; Shih-Hsu Huang; Rung-Bin Lin; Myung-Chul Kim (ICCAD, 2015)

Clock Period Minimization with Minimum Leakage Power. - Shih-Hsu Huang; Hua-Hsin Yeh; Yow-Tyng Nieh (ACM Trans. Design Autom. Electr. Syst., 2015)

Overview of the 2016 CAD contest at ICCAD. - Shih-Hsu Huang; Rung-Bin Lin; Myung-Chul Kim; Shigetoshi Nakatake (ICCAD, 2016)

Top-level activity-driven clock tree synthesis with clock skew variation considered. - Te-Jui Wang; Shih-Hsu Huang; Wei-Kai Cheng; Yih-Chih Chou (ISCAS, 2016)

Power-mode-aware buffer synthesis for low-power clock skew minimization. - Shih-Hsu Huang; Chun-Hua Cheng (IEICE Electron. Express, 2016)

Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs. - Chung-Han Chou; Hua-Hsin Yeh; Shih-Hsu Huang; Yow-Tyng Nieh; Shih-Chieh Chang; Yung-Tai Chang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

3D IC Memory BIST Controller Allocation for Test Time Minimization Under Power Constraints. - Yen-Chun Ko; Shih-Hsu Huang (ATS, 2017)

Overview of the 2017 CAD contest at ICCAD: Invited paper. - Myung-Chul Kim; Shih-Hsu Huang; Rung-Bin Lin; Shigetoshi Nakatake (ICCAD, 2017)

Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction. - Chung-Han Chou; Yenting Lai; Yi-Chun Chang; Chih-Yu Wang 002; Liang-Chia Cheng; Shih-Hsu Huang; Shih-Chieh Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction. - Wei-Kai Cheng; Jian-Kai Chen; Shih-Hsu Huang (ISOCC, 2018)

An Effective Approach for Building Low-Power General Activity-Driven Clock Trees. - Chen-Hsien Lin; Shih-Hsu Huang; Wei-Kai Cheng (ISOCC, 2018)

Keynote Talk: 3D Core-based SoC Testing for Low Power and TSV Count Minimization. - Shih-Hsu Huang (NoCArc@MICRO, 2018)

TSV-aware 3D test wrapper chain optimization. - Yu-Yi Wu; Shih-Hsu Huang (VLSI-DAT, 2018)

3D Test Wrapper Chain Optimization with I/O Cells Binding Considered. - Fan-Hsuan Tang; Hsu-Yu Kao; Shih-Hsu Huang; Jin-Fu Li 001 (3DIC, 2019)

A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs. - Wei-Hsuan Yang; Jin-Fu Li 001; Chun-Lung Hsu; Chi-Tien Sun; Shih-Hsu Huang (3DIC, 2019)

IC Camouflaging by Using Universal Gates under Timing Constraints. - Po-Chieh Chang; Shih-Hsu Huang (ICCE-TW, 2019)

Hardware Implementation for Multiple Activation Functions. - Chih-Hsiang Chang; Hsu-Yu Kao; Shih-Hsu Huang (ICCE-TW, 2019)

Softsign Function Hardware Implementation Using Piecewise Linear Approximation. - Chih-Hsiang Chang; En-Hui Zhang; Shih-Hsu Huang (ISPACS, 2019)

A Design Framework for Hardware Approximation of Deep Neural Networks. - Wei-Hung Lin; Hsu-Yu Kao; Shih-Hsu Huang (ISPACS, 2019)

Low-Power Small-Area $3 times 3$ Convolution Hardware Design. - Xin-Jia Chen; Shih-Hsu Huang (ICCE-TW, 2020)

Low-Power Hardware Architecture for Depthwise Separable Convolution Unit Design. - Shi-Rou Lin; Wei-Hung Lin; Shih-Hsu Huang; Chun-Lung Hsu; Chi-Tien Sun (ICCE-TW, 2020)

Low-Power Hardware Implementation for Parametric Rectified Linear Unit Function. - Yu-Hsuan Wu; Wei-Hung Lin; Shih-Hsu Huang (ICCE-TW, 2020)

A Simple Yet Accurate Method for The Unsigned Fixed-Width Multiplier Design. - En-Hui Zhang; Shih-Hsu Huang (ICCE-TW, 2020)

Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers. - Jui-Hung Hung; Shih-Hsu Huang; Chun-Hua Cheng; Hsu-Yu Kao; Wei-Kai Cheng (VTS, 2020)

A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations Into Partial Product Reduction Process. - Che-Wei Tung; Shih-Hsu Huang (IEEE Access, 2020)

Hardware Implementation for Fending off Side-Channel Attacks. - Yi-Liang Hong; Yui-Kai Weng; Shih-Hsu Huang (ICCE-TW, 2021)

Block-Based Compression for Reducing Indexing Cost of DNN Accelerators. - Yui-Kai Weng; Shih-Hsu Huang; Hsu-Yu Kao (ICCE-TW, 2021)

Low-Power Low-Error Fixed-Width Multiplier Design for Digital Signal Processing. - En-Hui Zhang; Shih-Hsu Huang (ICCE, 2021)

Hybrid Dynamic Fixed Point Quantization Methodology for AI Accelerators. - Wei-Hung Lin; Hsu-Yu Kao; Shih-Hsu Huang (ISOCC, 2021)

ECO Timing Optimization with Data Paths and Clock Paths Considered. - Jia-Xiang Tang; Shih-Hsu Huang; Jui-Hung Hung (ISPACS, 2021)

Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing. - Hsu-Yu Kao; Xin-Jia Chen; Shih-Hsu Huang (Sensors, 2021)

Block-Based Compression and Corresponding Hardware Circuits for Sparse Activations. - Yui-Kai Weng; Shih-Hsu Huang; Hsu-Yu Kao (Sensors, 2021)

A Behavior-Level Simulation Framework for RRAM-Based Deep Learning Accelerators with Flexible Architecture Configurations. - Hsu-Yu Kao; Shih-Hsu Huang (AICAS, 2022)

Network Pruning by Feature Map Sharing with K-Means Clustering. - De-Yang Chiu; Shih-Hsu Huang (ICCE-TW, 2022)

A Reinforcement Learning Methodology for The Search of SRAM CIM-based Accelerator Configuration. - Bo-Xi Lai; Shih-Hsu Huang; Hsu-Yu Kao (ICCE-TW, 2022)

Design and Dataflow for Multibit SRAM-Based MAC Operations. - Chuan-Han Cheng; Shih-Hsu Huang; Jin-Fu Li 001 (ISOCC, 2022)

Dataflow and Hardware Design for The Sharing of Feature Maps. - De-Yang Chiu; Shih-Hsu Huang (ISOCC, 2022)

Hardware Trojans of Computing-In-Memories: Issues and Methods. - Shih-Hsu Huang; Wei-Che Cheng; Jin-Fu Li 001 (DFT, 2023)

An Automatic Facial Analysis System for The Detection of Pediatric Obstructive Sleep Apnea. - Chia-Jo Lin; Shih-Hsu Huang; Wan-Yi Hsueh; Wei-Chung Hsu; Chih-Wen Su (ICCE-Taiwan, 2023)

Fault-Tolerant Near-Memory MAC Design with Redundant Memories. - Hsin-Chen Lu; Shih-Hsu Huang (ICCE-Taiwan, 2023)

A Metal-Only ECO Algorithm for Improving Hardware Security with Gate Camouflaging. - Liang-Ying Su; Shih-Hsu Huang (ICCE-Taiwan, 2023)

Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs. - Meng-Shan Wu; Yen-Lin Chua; Jin-Fu Li 001; Yun-Ting Chuan; Shih-Hsu Huang (ITC-Asia, 2023)

Secure Control Logic Design for Dual Key Logic Locking. - Yi-Chen Chen; Shih-Hsu Huang (APCCAS, 2024)

Special Session: Enhancing Reliability in Digital Computing-in-Memory Architectures Through Approximation and Fault Tolerance Methods. - Shih-Hsu Huang; Chih-Li Hsiao; Wei-Che Cheng (DFT, 2024)

Automatic Tool for Translating Sum-of-Product Expressions into Behavior-Level CIM Circuits. - Ting-Hao Chen; Shih-Hsu Huang; Chuan-Han Cheng; Li-Der Jeng (ICCE-Taiwan, 2024)

Securing Finite State Machines through Obfuscation Modes and Diverse Flip-Flop Configurations. - Ya-Cheng Yu; Shih-Hsu Huang (ICCE-Taiwan, 2024)

Design Flow for Incorporating Camouflaged Logic Gates to Enhance Hardware Security While Considering Timing Closure. - Liang-Ying Su; Shih-Hsu Huang (ISCAS, 2024)

An Approximate Method for The Fault Tolerance of SRAM-Based Near-Memory Multiply-Accumulate Units. - Yung-Chieh Lin; Liang-Ying Su; Shih-Hsu Huang (ISPACS, 2024)

Guest Editorial: Toward Trustworthy AI: Advances in Circuits, Systems, and Applications. - Shih-Hsu Huang; Pin-Yu Chen; Stjepan Picek; Chip-Hong Chang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2024)

An Overview of Trustworthy AI: Advances in IP Protection, Privacy-Preserving Federated Learning, Security Verification, and GAI Safety Alignment. - Yue Zheng; Chip-Hong Chang; Shih-Hsu Huang; Pin-Yu Chen; Stjepan Picek (IEEE J. Emerg. Sel. Topics Circuits Syst., 2024)

A High-Performance Hardware Design for Polynomial Multiplication in the CRYSTALS-Kyber Algorithm. - Hsueh Chen; Hsiu-Wei Chen; Shih-Hsu Huang; Po-Yuan Chen (COOL CHIPS, 2025)

PAT-ViT: Token Pruning-based Adversarial Tuning for Robust Vision Transformers. - Yun-Hao Yang; Yuan-June Luo; Wan-Jung Chen; An-Yeu Andy Wu; Shih-Hsu Huang; Mladen Berekovic (ISCAS, 2025)

Hardware Trojan Design With Low Overhead and High Destructiveness for STT-MRAM-Based CIMs. - Wei-Che Cheng; Shih-Hsu Huang; Jin-Fu Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)