A technology mapping algorithm for CPLD architectures. - Shih-Liang Chen; TingTing Hwang; C. L. Liu 001 (FPT, 2002)

Digital Secure-Communication Using Robust Hyper-Chaotic Systems. - Shih-Liang Chen; Shu-Ming Chang; Wen-Wei Lin; TingTing Hwang (Int. J. Bifurc. Chaos, 2008)

A Fast Digital Chaotic Generator for Secure Communication. - Shih-Liang Chen; TingTing Hwang; Shu-Ming Chang; Wen-Wei Lin (Int. J. Bifurc. Chaos, 2010)

A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test. - Wen-Wen Hsieh; Shih-Liang Chen; I-Sheng Lin; TingTing Hwang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Randomness Enhancement Using Digitalized Modified Logistic Map. - Shih-Liang Chen; TingTing Hwang; Wen-Wei Lin (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A physical-location-aware fault redistribution for maximum IR-drop reduction. - Fu-Wei Chen; Shih-Liang Chen; Yung-Sheng Lin; TingTing Hwang (ASP-DAC, 2011)

Reliability analysis and improvement for multi-level non-volatile memories with soft information. - Shih-Liang Chen; Bo-Ru Ke; Jian-Nan Chen; Chih-Tsun Huang (DAC, 2011)

A Physical-Location-Aware X-Bit Redistribution for Maximum IR-Drop Reduction. - Fu-Wei Chen; Shih-Liang Chen; Yung-Sheng Lin; TingTing Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2012)