An output tracking delay-recycled clock skew-compensation and/or duty-cycle-correction circuit. - Shih-Nung Wei; Yi-Ming Wang; Jyun-Hua Peng (ISCAS, 2012)

A range extending delay-recycled clock skew-compensation and/or duty-cycle-correction circuit. - Shih-Nung Wei; Yi-Ming Wang; Jyun-Hua Peng; Yuandi Surya (VLSI-DAT, 2012)

Range Unlimited Delay-Interleaving and -Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit. - Yi-Ming Wang; Shih-Nung Wei (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Process/Voltage/Temperature-Variation-Aware Design and Comparative Study of Transition-Detector-Based Error-Detecting Latches for Timing-Error-Resilient Pipelined Systems. - Jinn-Shyan Wang; Shih-Nung Wei (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs. - Chien-Tung Liu; Zhe-Wei Chang; Shih-Nung Wei; Jinn-Shyan Wang; Tay-Jyi Lin (SoCC, 2018)