A novel framework for multilevel routing considering routability and performance. - Shih-Ping Lin 001; Yao-Wen Chang (ICCAD, 2002)

Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme. - Jai-Ming Lin; Yao-Wen Chang; Shih-Ping Lin 001 (IEEE Trans. Very Large Scale Integr. Syst., 2003)

MR: a new framework for multilevel full-chip routing. - Yao-Wen Chang; Shih-Ping Lin 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A Scan Matrix Design for Low Power Scan-Based Test. - Shih Ping Lin 001; Chung-Len Lee 001; Jwu E. Chen (Asian Test Symposium, 2005)

Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing. - Shih Ping Lin 001; Chung-Len Lee 001; Jwu E. Chen (Asian Test Symposium, 2005)

A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. - Shih Ping Lin 001; Chung-Len Lee 001; Jwu E. Chen; Ji-Jan Chen; Kun-Lun Luo; Wen Ching Wu (ITC, 2006)

A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. - Shih-Ping Lin 001; Chung-Len Lee 001; Jwu-E Chen; Ji-Jan Chen; Kun-Lun Luo; Wen Ching Wu (IEEE Trans. Very Large Scale Integr. Syst., 2007)