A 104μW EMI-resisting bandgap voltage reference achieving -20dB PSRR, and 5% DC shift under a 4dBm EMI level. - Shiheng Yang; Pui-In Mak; Rui Paulo Martins (APCCAS, 2014)

A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM. - Shiheng Yang; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (ISSCC, 2018)

A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS. - Jun Yin 001; Shiheng Yang; Haidong Yi; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (ISSCC, 2018)

A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur. - Zunsong Yang; Yong Chen 005; Shiheng Yang; Pui-In Mak; Rui Paulo Martins (ISSCC, 2019)

A 0.0056-mm2 -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs. - Shiheng Yang; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS. - Shiheng Yang; Jun Yin 001; Haidong Yi; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-µs Settling Time for Multi-ISM-Band ULP Radios. - Ka-Fai Un; Gengzhen Qi; Jun Yin 001; Shiheng Yang; Shupeng Yu; Chio-In Ieong; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector. - Zunsong Yang; Yong Chen 005; Shiheng Yang; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2020)

A Low Power Sample-and-Hold Circuit with Improved Dynamic Bias for Pipelined ADC. - Xiaodan Zhou; Zehao Li; Yujie Wang; Xiong Zhou; Shiheng Yang; Jiaxin Liu; Qiang Li 021 (APCCAS, 2021)

A 640×512 30μm Pixel Pitch 1.8mK-NETD 90.1dB-SNR Digital Read-out Integrated Circuit with Fully On-chip Image Algorithm Pixel-Level Calibration. - Yan Zeng; Shiheng Yang; Yueduo Liu; Zehao Li; Wengang Huang; Xiaozong Huang; Xiong Zhou; Jiaxin Liu; Qiang Li 021 (A-SSCC, 2021)

A Low-Power RC Oscillator with Offset and Path Delay Cancellation. - Yueduo Liu; Zihao Zhu; Rongxin Bao; Shiheng Yang; Jiaxin Liu; Xiong Zhou; Qiang Li 021 (ICTA, 2021)

Sampling and Comparator Speed-Enhancement Techniques for Near-Threshold SAR ADCs. - Bojun Hu; Sanfeng Zhang; Xiangxin Pan; Xiangyu Zhao; Zhaoming Ding; Xiong Zhou; Shiheng Yang; Qiang Li 021 (IEEE Open J. Circuits Syst., 2021)

A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS. - Shiheng Yang; Jun Yin 001; Tailong Xu; Taimo Yi; Pui-In Mak; Qiang Li 021; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 4.2-to-5.6 GHz Transformer-Based PMOS-only Stacked-gm VCO in 28-nm CMOS. - Mingkang Zhang; Zihao Zhu; Yueduo Liu; Zehao Zhang; Rongxin Bao; Jiahui Lin; Haovu Zhuang; Jiaxin Liu; Xiong Zhou; Shiheng Yang; Qiang Li 021 (ICTA, 2022)

Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop. - Yueduo Liu; Rongxin Bao; Zihao Zhu; Shiheng Yang; Xiong Zhou; Jun Yin 001; Pui-In Mak; Qiang Li 021 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up. - Zehao Zhang; Shiheng Yang; Yueduo Liu; Zihao Zhu; Jiahui Lin; Rongxin Bao; Tailong Xu; Zhizhan Yang; Mingkang Zhang; Jiaxin Liu; Xiong Zhou; Jun Yin 001; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network. - Yuchen Wei; Shiheng Yang; Yueduo Liu; Rongxin Bao; Zihao Zhu; Jiahui Lin; Zehao Zhang; Yong Chen 005; Jun Yin 001; Pui-In Mak; Qiang Li 021 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Noise Shaping SAR ADC with kT/C Noise Cancellation and Mismatch Error Shaping. - Tiange Yi; Zhenbing Li; Bing Du; Shiheng Yang; Jiaxin Liu (ICTA, 2024)

A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS. - Yueduo Liu; Zihao Zhu; Rongxin Bao; Jiahui Lin; Jun Yin 001; Qiang Li 021; Pui-In Mak; Shiheng Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 0.4μW/MHz Reference-Replication-Based RC Oscillator with Path-Delay and Comparator-Offset Cancellation Achieving 9.83ppm/°C from -40 to 125°C. - Yueduo Liu; Zihao Zhu; Xinyu Yang; Rongxin Bao; Zehao Zhang; Hongshuai Zhang; Jiaxin Liu; Zheng Wang; Mingkang Zhang; Na Yan; Jun Yin 001; Pui-In Mak; et al. (ISSCC, 2025)

18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW. - Han Zhao; Xuanhao Zhang; Qijin Deng; Jialin Hu; Zhenbing Li; Shiheng Yang; Jiaxin Liu (ISSCC, 2025)

Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction. - Tailong Xu; Haoran Li; Xi Meng; Xiangxun Zhan; Yatao Peng; Jun Yin 001; Shiheng Yang; Chao Fan; Zhixiang Huang; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL. - Jingrun Song; Xinyu Yang; Jiaxu Liu; Yueduo Liu; Zihao Zhu; Zhengxuan Han; Zehao Zhang; Jiaxin Liu; Hongshuai Zhang; Jun Yin 001; Pui-In Mak; Shiheng Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 6.8-14.4GHz Calibration-Free Fractional-N RO-Based Harmonic-Mixing Frequency Synthesizer Achieving -80.7dBc Fractional Spur. - Zonglin Ye; Hongyang Zhang; Yuxuan Sun; Xinlin Geng; Qian Xie 002; Shiheng Yang; Zheng Wang 050 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)