Environment-Adaptable Efficient Optimization for Programming of Reconfigurable Radio Frequency (RF) Receivers. - Minhee Jun; Rohit Negi; Jun Tao 001; Ying-Chih Wang; Shihui Yin; Tamal Mukherjee; Xin Li 001; Lawrence T. Pileggi (MILCOM, 2014)

Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data. - Ying-Chih Wang; Shihui Yin; Minhee Jun; Xin Li 001; Lawrence T. Pileggi; Tamal Mukherjee; Rohit Negi (ASP-DAC, 2015)

Phase Noise Impairment and Environment-Adaptable Fast (EAF) Optimization for Programming of Reconfigurable Radio Frequency (RF) Receivers. - Minhee Jun; Rohit Negi; Shihui Yin; Fa Wang; Megha Sunny; Tamal Mukherjee; Xin Li 001 (GLOBECOM, 2015)

Re-thinking polynomial optimization: Efficient programming of reconfigurable radio frequency (RF) systems by convexification. - Fa Wang; Shihui Yin; Minhee Jun; Xin Li 001; Tamal Mukherjee; Rohit Negi; Larry T. Pileggi (ASP-DAC, 2016)

Minimizing area and energy of deep learning hardware design using collective low precision and structured compression. - Shihui Yin; Gaurav Srivastava 001; Shreyas K. Venkataramanaiah; Chaitali Chakrabarti; Visar Berisha; Jae-sun Seo (ACSSC, 2017)

Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations. - Shihui Yin; Shreyas K. Venkataramanaiah; Gregory K. Chen; Ram Krishnamurthy 001; Yu Cao 001; Chaitali Chakrabarti; Jae-sun Seo (BioCAS, 2017)

Designing ECG-based physical unclonable function for security of wearable devices. - Shihui Yin; Chisung Bae; Sang Joon Kim; Jae-sun Seo (EMBC, 2017)

Efficient programming of reconfigurable radio frequency (RF) systems. - Mohamed Baker Alawieh; Fa Wang; Jun Tao 001; Shihui Yin; Minhee Jun; Xin Li 001; Tamal Mukherjee; Rohit Negi (ICCAD, 2017)

XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. - Xiaoyu Sun 001; Shihui Yin; Xiaochen Peng; Rui Liu 005; Jae-sun Seo; Shimeng Yu (DATE, 2018)

A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks. - Shihui Yin; Xiaoyu Sun 001; Shimeng Yu; Jae-sun Seo; Chaitali Chakrabarti (SiPS, 2018)

Environment-Adaptable Fast Multi-Resolution (EAF-MR) optimization in large-scale RF-FPGA systems. - Minhee Jun; Rohit Negi; Shihui Yin; Mohamed Baker Alawieh; Fa Wang; Megha Sunny; Tamal Mukherjee; Xin Li 001 (EURASIP J. Wirel. Commun. Netw., 2018)

Vesti: An In-Memory Computing Processor for Deep Neural Networks Acceleration. - Zhewei Jiang; Shihui Yin; Minkyu Kim 001; Tushar Gupta; Mingoo Seok; Jae-sun Seo (ACSSC, 2019)

C3SRAM: In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing. - Zhewei Jiang; Shihui Yin; Jae-Sun Seo; Mingoo Seok (ESSCIRC, 2019)

Automatic Compiler Based FPGA Accelerator for CNN Training. - Shreyas Kolala Venkataramanaiah; Yufei Ma 002; Shihui Yin; Eriko Nurvitadhi; Aravind Dasu; Yu Cao 001; Jae-sun Seo (FPL, 2019)

XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism. - Zhewei Jiang; Shihui Yin; Jae-sun Seo; Mingoo Seok (ACM Great Lakes Symposium on VLSI, 2019)

Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks. - Gaurav Srivastava 001; Deepak Kadetotad; Shihui Yin; Visar Berisha; Chaitali Chakrabarti; Jae-sun Seo (ICASSP, 2019)

Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays. - Shruti R. Kulkarni; Deepak Vinayak Kadetotad; Shihui Yin; Jae-Sun Seo; Bipin Rajendran (ICECS, 2019)

ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression. - Sai Kiran Cherupally; Gaurav Srivastava 001; Shihui Yin; Deepak Kadetotad; Chisung Bae; Sang Joon Kim; Jae-sun Seo (ISCAS, 2019)

K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM. - Jyotishman Saikia; Shihui Yin; Zhewei Jiang; Mingoo Seok; Jae-sun Seo (ISLPED, 2019)

Inference engine benchmarking across technological platforms from CMOS to RRAM. - Xiaochen Peng; Minkyu Kim 001; Xiaoyu Sun 001; Shihui Yin; Titash Rakshit; Ryan M. Hatcher; Jorge A. Kittl; Jae-sun Seo; Shimeng Yu (MEMSYS, 2019)

High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS. - Shihui Yin; Xiaoyu Sun 001; Shimeng Yu; Jae-sun Seo (CoRR, 2019)

A 1.06- $ mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring. - Shihui Yin; Minkyu Kim 001; Deepak Kadetotad; Yang Liu; Chisung Bae; Sang Joon Kim; Yu Cao 001; Jae-sun Seo (IEEE J. Solid State Circuits, 2019)

Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning. - Shihui Yin; Jae-sun Seo; Yulhwa Kim; Xu Han; Hugh J. Barnaby; Shimeng Yu; Yandong Luo; Wangxin He; Xiaoyu Sun 001; Jae-Joon Kim (IEEE Micro, 2019)

An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays. - Shruti R. Kulkarni; Shihui Yin; Jae-sun Seo; Bipin Rajendran (DATE, 2020)

FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory. - Shreyas K. Venkataramanaiah; Han-Sok Suh; Shihui Yin; Eriko Nurvitadhi; Aravind Dasu; Yu Cao 001; Jae-Sun Seo (ICCAD, 2020)

Efficient and Modularized Training on FPGA for Real-time Applications. - Shreyas Kolala Venkataramanaiah; Xiaocong Du; Zheng Li 020; Shihui Yin; Yu Cao 001; Jae-sun Seo (IJCAI, 2020)

Deep Neural Network Training Accelerator Designs in ASIC and FPGA. - Shreyas K. Venkataramanaiah; Shihui Yin; Yu Cao 001; Jae-Sun Seo (ISOCC, 2020)

A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation. - Sai Kiran Cherupally; Shihui Yin; Deepak Kadetotad; Chisung Bae; Sang Joon Kim; Jae-sun Seo (IEEE J. Solid State Circuits, 2020)

C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism. - Zhewei Jiang; Shihui Yin; Jae-Sun Seo; Mingoo Seok (IEEE J. Solid State Circuits, 2020)

An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition. - Deepak Kadetotad; Shihui Yin; Visar Berisha; Chaitali Chakrabarti; Jae-sun Seo (IEEE J. Solid State Circuits, 2020)

XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks. - Shihui Yin; Zhewei Jiang; Jae-Sun Seo; Mingoo Seok (IEEE J. Solid State Circuits, 2020)

ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression. - Sai Kiran Cherupally; Shihui Yin; Deepak Kadetotad; Gaurav Srivastava 001; Chisung Bae; Sang Joon Kim; Jae-sun Seo (IEEE Trans. Biomed. Circuits Syst., 2020)

Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks. - Shihui Yin; Zhewei Jiang; Minkyu Kim 001; Tushar Gupta; Mingoo Seok; Jae-Sun Seo (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Energy-Efficient Circuit and Architecture Designs for Intelligent Systems. - Shihui Yin (2020)

Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks. - Sai Kiran Cherupally; Adnan Siraj Rakin; Shihui Yin; Mingoo Seok; Deliang Fan; Jae-sun Seo (DAC, 2021)

Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design. - Jyotishman Saikia; Shihui Yin; Sai Kiran Cherupally; Bo Zhang 105; Jian Meng; Mingoo Seok; Jae-Sun Seo (DATE, 2021)

Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing. - Wangxin He; Wonbo Shim; Shihui Yin; Xiaoyu Sun 001; Deliang Fan; Shimeng Yu; Jae-sun Seo (IRPS, 2021)

PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference. - Shihui Yin; Bo Zhang 105; Minkyu Kim 001; Jyotishman Saikia; Soonwan Kwon; Sungmeen Myung; Hyunsoo Kim; Sang Joon Kim; Mingoo Seok; Jae-sun Seo (VLSI Circuits, 2021)

Compact Modeling of IGZO-based CAA-FETs with Time-zero-instability and BTI Impact on Device and Capacitor-less DRAM Retention Reliability. - Jingrui Guo; Ying Sun; Lingfei Wang; Xinlv Duan; Kailiang Huang; Zhaogui Wang; Junxiao Feng; Qian Chen; Shijie Huang; Lihua Xu; Di Geng; Guangfan Jiao; et al. (VLSI Technology and Circuits, 2022)

Vertical Channel-All-Around (CAA) IGZO FET under 50 nm CD with High Read Current of 32.8 μA/μm (Vth + 1 V), Well-performed Thermal Stability up to 120 ℃ for Low Latency, High-density 2T0C 3D DRAM Application. - Kailiang Huang; Xinlv Duan; Junxiao Feng; Ying Sun; Congyan Lu; Chuanke Chen; Guangfan Jiao; Xinpeng Lin; Jinhai Shao; Shihui Yin; Jiazhen Sheng; Zhaogui Wang; et al. (VLSI Technology and Circuits, 2022)

Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection. - Sai Kiran Cherupally; Jian Meng; Adnan Siraj Rakin; Shihui Yin; Mingoo Seok; Deliang Fan; Jae-Sun Seo (IEEE Des. Test, 2022)

Efficient continual learning at the edge with progressive segmented training. - Xiaocong Du; Shreyas Kolala Venkataramanaiah; Zheng Li 020; Han-Sok Suh; Shihui Yin; Gokul Krishnan; Frank Liu 001; Jae-sun Seo; Yu Cao 001 (Neuromorph. Comput. Eng., 2022)

PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference. - Bo Zhang 105; Shihui Yin; Minkyu Kim 001; Jyotishman Saikia; Soonwan Kwon; Sungmeen Myung; Hyunsoo Kim; Sang Joon Kim; Jae-Sun Seo; Mingoo Seok (IEEE J. Solid State Circuits, 2023)