High-performance architecture for dynamically updatable packet classification on FPGA. - Yun Rock Qu; Shijie Zhou 001; Viktor K. Prasanna (ANCS, 2013)

Scalable Many-Field Packet Classification on Multi-core Processors. - Yun Qu 001; Shijie Zhou 001; Viktor K. Prasanna (SBAC-PAD, 2013)

Energy performance of FPGAs on PERFECT suite kernels. - Sanmukh R. Kuppannagari; Ren Chen; Andrea Sanny; Shreyas G. Singapura; Geoffrey Phi C. Tran; Shijie Zhou 001; Yusong Hu; Stephen P. Crago; Viktor K. Prasanna (HPEC, 2014)

High-performance packet classification on GPU. - Shijie Zhou 001; Shreyas G. Singapura; Viktor K. Prasanna (HPEC, 2014)

Performance modeling and optimizations for decomposition-based large-scale packet classification on multi-core processors. - Yun Rock Qu; Shijie Zhou 001; Viktor K. Prasanna (HPSR, 2014)

A flexible and scalable high-performance OpenFlow switch on heterogeneous SoC platforms. - Shijie Zhou 001; Weirong Jiang; Viktor K. Prasanna (IPCCC, 2014)

400 Gbps energy-efficient multi-field packet classification on FPGA. - Shijie Zhou 001; Sihan Zhao; Viktor K. Prasanna (ReConFig, 2014)

High-Performance Traffic Classification on GPU. - Shijie Zhou 001; Prashant Rao Nittoor; Viktor K. Prasanna (SBAC-PAD, 2014)

A programmable and scalable openflow switch using heterogeneous soc platforms. - Shijie Zhou 001; Weirong Jiang; Viktor K. Prasanna (HotSDN, 2014)

Multi-core implementation of decomposition-based packet classification algorithms. - Shijie Zhou 001; Yun Rock Qu; Viktor K. Prasanna (J. Supercomput., 2014)

Optimizing Many-field Packet Classification on FPGA, Multi-core General Purpose Processor, and GPU. - Yun Rock Qu; Hao H. Zhang; Shijie Zhou 001; Viktor K. Prasanna (ANCS, 2015)

Large-scale packet classification on FPGA. - Shijie Zhou 001; Yun Rock Qu; Viktor K. Prasanna (ASAP, 2015)

Scalable GPU-Accelerated IPv6 Lookup Using Hierarchical Perfect Hashing. - Shijie Zhou 001; Viktor K. Prasanna (GLOBECOM, 2015)

High-Throughput Online Hash Table on FPGA. - Da Tong; Shijie Zhou 001; Viktor K. Prasanna (IPDPS Workshops, 2015)

Accelerating Large-Scale Single-Source Shortest Path on FPGA. - Shijie Zhou 001; Charalampos Chelmis; Viktor K. Prasanna (IPDPS Workshops, 2015)

Optimizing memory performance for FPGA implementation of pagerank. - Shijie Zhou 001; Charalampos Chelmis; Viktor K. Prasanna (ReConFig, 2015)

A Decomposition-Based Approach for Scalable Many-Field Packet Classification on Multi-core Processors. - Yun Rock Qu; Shijie Zhou 001; Viktor K. Prasanna (Int. J. Parallel Program., 2015)

Packet Classification on Multi-core Platforms. - Yun Rock Qu; Shijie Zhou 001; Viktor K. Prasanna (Handbook on Data Centers, 2015)

High-Throughput and Energy-Efficient Graph Processing on FPGA. - Shijie Zhou 001; Charalampos Chelmis; Viktor K. Prasanna (FCCM, 2016)

Quickly finding a truss in a haystack. - Oded Green; James Fox; Euna Kim; Federico Busato; Nicola Bombieri; Kartik Lakhotia; Shijie Zhou 001; Shreyas G. Singapura; Hanqing Zeng; Rajgopal Kannan; Viktor K. Prasanna; David A. Bader (HPEC, 2017)

Design and implementation of parallel PageRank on multicore platforms. - Shijie Zhou 001; Kartik Lakhotia; Shreyas G. Singapura; Hanqing Zeng; Rajgopal Kannan; Viktor K. Prasanna; James Fox; Euna Kim; Oded Green; David A. Bader (HPEC, 2017)

Accelerating low rank matrix completion on FPGA. - Shijie Zhou 001; Rajgopal Kannan; Viktor K. Prasanna (ReConFig, 2017)

Accelerating Graph Analytics on CPU-FPGA Heterogeneous Platform. - Shijie Zhou 001; Viktor K. Prasanna (SBAC-PAD, 2017)

bitFA: A Novel Data Structure for Fast and Update-friendly Regular Expression Matching. - Zhe Fu; Shijie Zhou 001; Jun Li 003 (SIGCOMM Posters and Demos, 2017)

An FPGA framework for edge-centric graph processing. - Shijie Zhou 001; Rajgopal Kannan; Hanqing Zeng; Viktor K. Prasanna (CF, 2018)

FASTCF: FPGA-based Accelerator for STochastic-Gradient-Descent-based Collaborative Filtering. - Shijie Zhou 001; Rajgopal Kannan; Yu Min; Viktor K. Prasanna (FPGA, 2018)

HitGraph: High-throughput Graph Processing Framework on FPGA. - Shijie Zhou 001; Rajgopal Kannan; Viktor K. Prasanna; Guna Seetharaman; Qing Wu (IEEE Trans. Parallel Distributed Syst., 2019)

Accelerating Stochastic Gradient Descent Based Matrix Factorization on FPGA. - Shijie Zhou 001; Rajgopal Kannan; Viktor K. Prasanna (IEEE Trans. Parallel Distributed Syst., 2020)