A Survey of Recent Attacks and Mitigation on FPGA Systems. - Shijin Duan; Wenhao Wang 001; Yukui Luo; Xiaolin Xu 001 (ISVLSI, 2021)

HDCOG: A Lightweight Hyperdimensional Computing Framework with Feature Extraction. - Shijin Duan; Xiaolin Xu 001 (NANOARCH, 2021)

Deep Neural Network Security From a Hardware Perspective. - Tong Zhou 002; Yuheng Zhang; Shijin Duan; Yukui Luo; Xiaolin Xu 001 (NANOARCH, 2021)

LeHDC: learning-based hyperdimensional computing classifier. - Shijin Duan; Yejia Liu; Shaolei Ren; Xiaolin Xu 001 (DAC, 2022)

HDLock: exploiting privileged encoding to protect hyperdimensional computing models against IP stealing. - Shijin Duan; Shaolei Ren; Xiaolin Xu 001 (DAC, 2022)

NNReArch: A Tensor Program Scheduling Framework Against Neural Network Architecture Reverse Engineering. - Yukui Luo; Shijin Duan; Cheng Gongye; Yunsi Fei; Xiaolin Xu 001 (FCCM, 2022)

An Integrity Checking Framework for AXI Protocol in Multi-tenant FPGA. - Yukui Luo; Yuheng Zhang; Shijin Duan; Xiaolin Xu 001 (FPGA, 2022)

A Cautionary Note on Building Multi-tenant Cloud-FPGA as a Secure Infrastructure. - Yukui Luo; Yuheng Zhang; Shijin Duan; Xiaolin Xu 001 (FPT, 2022)

A Brain-Inspired Low-Dimensional Computing Classifier for Inference on Tiny Devices. - Shijin Duan; Xiaolin Xu 001; Shaolei Ren (CoRR, 2022)

FPGAPRO: A Defense Framework Against Crosstalk-Induced Secret Leakage in FPGA. - Yukui Luo; Shijin Duan; Xiaolin Xu 001 (ACM Trans. Design Autom. Electr. Syst., 2022)

PASNet: Polynomial Architecture Search Framework for Two-party Computation-based Secure Neural Network Deployment. - Hongwu Peng; Shanglin Zhou; Yukui Luo; Nuo Xu; Shijin Duan; Ran Ran; Jiahui Zhao; Chenghong Wang; Tong Geng; Wujie Wen; Xiaolin Xu 001; Caiwen Ding (DAC, 2023)

MirrorNet: A TEE-Friendly Framework for Secure On-Device DNN Inference. - Ziyu Liu; Yukui Luo; Shijin Duan; Tong Zhou 002; Xiaolin Xu 001 (ICCAD, 2023)

VertexSerum: Poisoning Graph Neural Networks for Link Inference. - Ruyi Ding; Shijin Duan; Xiaolin Xu 001; Yunsi Fei (ICCV, 2023)

Achieving Certified Robustness for Brain-Inspired Low-Dimensional Computing Classifiers. - Fangfang Yang; Shijin Duan; Xiaolin Xu 001; Shaolei Ren (INFOCOM Workshops, 2023)

AQ2PNN: Enabling Two-party Privacy-Preserving Deep Neural Network Inference with Adaptive Quantization. - Yukui Luo; Nuo Xu; Hongwu Peng; Chenghong Wang; Shijin Duan; Kaleel Mahmood; Wujie Wen; Caiwen Ding; Xiaolin Xu 001 (MICRO, 2023)

RRNet: Towards ReLU-Reduced Neural Network for Two-party Computation Based Private Inference. - Hongwu Peng; Shanglin Zhou; Yukui Luo; Nuo Xu; Shijin Duan; Ran Ran; Jiahui Zhao; Shaoyi Huang; Xi Xie; Chenghong Wang; Tong Geng; Wujie Wen; et al. (CoRR, 2023)

MetaLDC: Meta Learning of Low-Dimensional Computing Classifiers for Fast On-Device Adaption. - Yejia Liu; Shijin Duan; Xiaolin Xu 001; Shaolei Ren (CoRR, 2023)

MicroVSA: An Ultra-Lightweight Vector Symbolic Architecture-based Classifier Library for Always-On Inference on Tiny Microcontrollers. - Nuntipat Narkthong; Shijin Duan; Shaolei Ren; Xiaolin Xu 001 (ASPLOS (2), 2024)

GraphCroc: Cross-Correlation Autoencoder for Graph Structural Reconstruction. - Shijin Duan; Ruyi Ding; Jiaxing He; Aidong Adam Ding; Yunsi Fei; Xiaolin Xu 001 (NeurIPS, 2024)

Scheduled Knowledge Acquisition on Lightweight Vector Symbolic Architectures for Brain-Computer Interfaces. - Yejia Liu; Shijin Duan; Xiaolin Xu 001; Shaolei Ren (CoRR, 2024)

SSNet: A Lightweight Multi-Party Computation Scheme for Practical Privacy-Preserving Machine Learning Service in the Cloud. - Shijin Duan; Chenghong Wang; Hongwu Peng; Yukui Luo; Wujie Wen; Caiwen Ding; Xiaolin Xu 001 (CoRR, 2024)

Towards Vector Optimization on Low-Dimensional Vector Symbolic Architecture. - Shijin Duan; Yejia Liu; Gaowen Liu; Ramana Rao Kompella; Shaolei Ren; Xiaolin Xu 001 (CPAL, 2025)

ProDiF: Protecting Domain-Invariant Features to Secure Pre-Trained Models Against Extraction. - Tong Zhou 002; Shijin Duan; Gaowen Liu; Charles Fleming; Ramana Rao Kompella; Shaolei Ren; Xiaolin Xu 001 (CoRR, 2025)