Formal Methods for Validation and Test Point Prioritization in Railway Signaling Logic. - Shiladitya Ghosh; Arindam Das; Nirvik Basak; Pallab Dasgupta; Alok Katiyar (IEEE Trans. Intell. Transp. Syst., 2017)

Input Elimination Transformations for Scalable Verification and Trace Reconstruction. - Raj Kumar Gajavelly; Jason Baumgartner; Alexander Ivrii; Robert L. Kanzelman; Shiladitya Ghosh (FMCAD, 2019)