Metal-Oxide RRAM. - H.-S. Philip Wong; Heng-Yuan Lee; Shimeng Yu; Yu-Sheng Chen; Yi Wu 016; Pang-Shiu Chen; Byoungil Lee; Frederick T. Chen; Ming-Jinn Tsai (Proc. IEEE, 2012)

Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture. - Cong Xu 002; Dimin Niu; Shimeng Yu; Yuan Xie 001 (ASP-DAC, 2014)

Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. - Zihan Xu; Abinash Mohanty; Pai-Yu Chen; Deepak Kadetotad; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Shimeng Yu; Jae-sun Seo; Yu Cao 001 (BICA, 2014)

Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. - Deepak Kadetotad; Zihan Xu; Abinash Mohanty; Pai-Yu Chen; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Shimeng Yu; Yu Cao 001; Jae-sun Seo (BioCAS, 2014)

Reliability-aware cross-point resistive memory design. - Cong Xu 002; Dimin Niu; Yang Zheng; Shimeng Yu; Yuan Xie 001 (ACM Great Lakes Symposium on VLSI, 2014)

Architecting 3D vertical resistive memory for next-generation storage systems. - Cong Xu 002; Pai-Yu Chen; Dimin Niu; Yang Zheng; Shimeng Yu; Yuan Xie 001 (ICCAD, 2014)

Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture. - Jinfeng Kang; Bin Gao 006; Bing Chen; Peng Huang 004; Feifei Zhang; Xiaoyan Liu; Hong-Yu Chen; Zizhen Jiang; H.-S. Philip Wong; Shimeng Yu (ISCAS, 2014)

Orientation classification by a winner-take-all network with oxide RRAM based synaptic devices. - Shimeng Yu (ISCAS, 2014)

Overview of resistive switching memory (RRAM) switching mechanism and device modeling. - Shimeng Yu (ISCAS, 2014)

Design guidelines for 3D RRAM cross-point architecture. - Shimeng Yu; Yexin Deng; Bin Gao 006; Peng Huang 004; Bing Chen; Xiaoyan Liu; Jinfeng Kang; Hong-Yu Chen; Zizhen Jiang; H.-S. Philip Wong (ISCAS, 2014)

Design considerations of synaptic device for neuromorphic computing. - Shimeng Yu; Duygu Kuzum; H.-S. Philip Wong (ISCAS, 2014)

Integration of threshold logic gates with RRAM devices for energy efficient and robust operation. - Jinghua Yang; Niranjan Kulkarni; Shimeng Yu; Sarma B. K. Vrudhula (NANOARCH, 2014)

Technological exploration of RRAM crossbar array for matrix-vector multiplication. - Peng Gu; Boxun Li; Tianqi Tang 001; Shimeng Yu; Yu Cao 001; Yu Wang 002; Huazhong Yang (ASP-DAC, 2015)

Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. - Pai-Yu Chen; Deepak Kadetotad; Zihan Xu; Abinash Mohanty; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Jae-sun Seo; Yu Cao 001; Shimeng Yu (DATE, 2015)

On-chip Sparse Learning with Resistive Cross-point Array Architecture. - Shimeng Yu; Yu Cao 001 (ACM Great Lakes Symposium on VLSI, 2015)

Exploiting resistive cross-point array for compact design of physical unclonable function. - Pai-Yu Chen; Runchen Fang; Rui Liu 005; Chaitali Chakrabarti; Yu Cao 001; Shimeng Yu (HOST, 2015)

Overcoming the challenges of crossbar resistive memory architectures. - Cong Xu 002; Dimin Niu; Naveen Muralimanohar; Rajeev Balasubramonian; Tao Zhang 032; Shimeng Yu; Yuan Xie 001 (HPCA, 2015)

Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. - Pai-Yu Chen; Binbin Lin; I-Ting Wang; Tuo-Hung Hou; Jieping Ye; Sarma B. K. Vrudhula; Jae-sun Seo; Yu Cao 001; Shimeng Yu (ICCAD, 2015)

Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings. - Manqing Mao; Yu Cao 001; Shimeng Yu; Chaitali Chakrabarti (ICCD, 2015)

RRAM based synaptic devices for neuromorphic visual systems. - Jinfeng Kang; Bin Gao 006; Peng Huang 004; Lifeng Liu; Xiaoyan Liu; H. Y. Yu; Shimeng Yu; H.-S. Philip Wong (DSP, 2015)

Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design. - Scott Zuloaga; Rui Liu 005; Pai-Yu Chen; Shimeng Yu (ISCAS, 2015)

Programming strategies to improve energy efficiency and reliability of ReRAM memory systems. - Manqing Mao; Yu Cao 001; Shimeng Yu; Chaitali Chakrabarti (SiPS, 2015)

Device and System Level Design Considerations for Analog-Non-Volatile-Memory Based Neuromorphic Architectures. - Sukru Burc Eryilmaz; Duygu Kuzum; Shimeng Yu; H.-S. Philip Wong (CoRR, 2015)

Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. - Deepak Kadetotad; Zihan Xu; Abinash Mohanty; Pai-Yu Chen; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Shimeng Yu; Yu Cao 001; Jae-sun Seo (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design. - Cong Xu 002; Dimin Niu; Yang Zheng; Shimeng Yu; Yuan Xie 001 (ACM Trans. Design Autom. Electr. Syst., 2015)

MNSIM: Simulation platform for memristor-based neuromorphic computing system. - Lixue Xia; Boxun Li; Tianqi Tang 001; Peng Gu; Xiling Yin; Wenqin Huangfu; Pai-Yu Chen; Shimeng Yu; Yu Cao 001; Yu Wang 002; Yuan Xie 001; Huazhong Yang (DATE, 2016)

Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM. - Robert Karam; Rui Liu 005; Pai-Yu Chen; Shimeng Yu; Swarup Bhunia (ACM Great Lakes Symposium on VLSI, 2016)

A highly reliable and tamper-resistant RRAM PUF: Design and experimental validation. - Rui Liu 005; Huaqiang Wu; Yachun Pang; He Qian; Shimeng Yu (HOST, 2016)

Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing. - Pai-Yu Chen; Jae-sun Seo; Yu Cao 001; Shimeng Yu (ICCAD, 2016)

Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing. - Pai-Yu Chen; Shimeng Yu (ISCAS, 2016)

Design of a reliable RRAM-based PUF for compact hardware security primitives. - Ayush Shrivastava; Pai-Yu Chen; Yu Cao 001; Shimeng Yu; Chaitali Chakrabarti (ISCAS, 2016)

Optimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniques. - Manqing Mao; Yu Cao 001; Shimeng Yu; Chaitali Chakrabarti (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication. - Lixue Xia; Peng Gu; Boxun Li; Tianqi Tang 001; Xiling Yin; Wenqin Huangfu; Shimeng Yu; Yu Cao 001; Yu Wang 002; Huazhong Yang (J. Comput. Sci. Technol., 2016)

Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning. - Pai-Yu Chen; Ligang Gao; Shimeng Yu (IEEE Trans. Multi Scale Comput. Syst., 2016)

Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array. - Pai-Yu Chen; Zhiwei Li 008; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Resistive Random Access Memory (RRAM) - Shimeng Yu (Morgan & Claypool Publishers, 2016)

Extending 1kb RRAM array from weak PUF to strong PUF by employment of SHA module. - Rui Liu 005; Huaqiang Wu; Yachun Pang; He Qian; Shimeng Yu (AsianHOST, 2017)

1T2R: A novel memory cell design to resolve single-event upset in RRAM arrays. - Amr M. S. Tosson; Shimeng Yu; Mohab H. Anis; Lan Wei (ASICON, 2017)

Analyzing inference robustness of RRAM synaptic array in low-precision neural network. - Rui Liu 005; Heng-Yuan Lee; Shimeng Yu (ESSDERC, 2017)

Mitigating the Effect of Reliability Soft-errors of RRAM Devices on the Performance of RRAM-based Neuromorphic Systems. - Amr M. S. Tosson; Shimeng Yu; Mohab H. Anis; Lan Wei (ACM Great Lakes Symposium on VLSI, 2017)

Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array. - Rui Liu 005; Pai-Yu Chen; Shimeng Yu (ISCAS, 2017)

Analysis of RRAM Reliability Soft-Errors on the Performance of RRAM-Based Neuromorphic Systems. - Amr M. S. Tosson; Shimeng Yu; Mohab H. Anis; Lan Wei (ISVLSI, 2017)

Improving efficiency in sparse learning with the feedforward inhibitory motif. - Zihan Xu; Steven Skorheim; Ming Tu; Visar Berisha; Shimeng Yu; Jae-sun Seo; Maxim Bazhenov; Yu Cao 001 (Neurocomputing, 2017)

Energy-Efficient Adaptive Computing With Multifunctional Memory. - Wenchao Qian; Pai-Yu Chen; Robert Karam; Ligang Gao; Swarup Bhunia; Shimeng Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System. - Manqing Mao; Pai-Yu Chen; Shimeng Yu; Chaitali Chakrabarti (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network. - Xiaoyu Sun 001; Rui Liu 005; Yi-Ju Chen; Hsiao-Yun Chiu; Wei-Hao Chen; Meng-Fan Chang; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Study of the Effect of RRAM Reliability Soft Errors on the Performance of RRAM-Based Neuromorphic Systems. - Amr M. S. Tosson; Shimeng Yu; Mohab H. Anis; Lan Wei (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Benchmark of RRAM based Architectures for Dot-Product Computation. - Xiaochen Peng; Shimeng Yu (APCCAS, 2018)

Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. - Xiaoyu Sun 001; Xiaochen Peng; Pai-Yu Chen; Rui Liu 005; Jae-sun Seo; Shimeng Yu (ASP-DAC, 2018)

Parallelizing SRAM arrays with customized bit-cell for binary neural networks. - Rui Liu 005; Xiaochen Peng; Xiaoyu Sun 001; Win-San Khwa; Xin Si; Jia-Jing Chen; Jia-Fang Li; Meng-Fan Chang; Shimeng Yu (DAC, 2018)

XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. - Xiaoyu Sun 001; Shihui Yin; Xiaochen Peng; Rui Liu 005; Jae-sun Seo; Shimeng Yu (DATE, 2018)

Reliability perspective of resistive synaptic devices on the neuromorphic system performance. - Pai-Yu Chen; Shimeng Yu (IRPS, 2018)

Design Considerations of Selector Device in Cross-Point RRAM Array for Neuromorphic Computing. - Jiyong Woo; Xiaochen Peng; Shimeng Yu (ISCAS, 2018)

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. - Win-San Khwa; Jia-Jing Chen; Jia-Fang Li; Xin Si; En-Yu Yang; Xiaoyu Sun 001; Rui Liu 005; Pai-Yu Chen; Qiang Li 021; Shimeng Yu; Meng-Fan Chang (ISSCC, 2018)

A Versatile ReRAM-based Accelerator for Convolutional Neural Networks. - Manqing Mao; Xiaoyu Sun 001; Xiaochen Peng; Shimeng Yu; Chaitali Chakrabarti (SiPS, 2018)

A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks. - Shihui Yin; Xiaoyu Sun 001; Shimeng Yu; Jae-sun Seo; Chaitali Chakrabarti (SiPS, 2018)

Special session on reliability and vulnerability of neuromorphic computing systems. - Shimeng Yu; Chenchen Liu; Wujie Wen; Yiran Chen 001 (VTS, 2018)

Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain. - Chetan Singh Thakur; Jamal Molin; Gert Cauwenberghs; Giacomo Indiveri; Kundan Kumar; Ning Qiao; Johannes Schemmel; Runchun Wang; Elisabetta Chicca; Jennifer Olson Hasler; Jae-sun Seo; Shimeng Yu; et al. (CoRR, 2018)

Neuro-Inspired Computing With Emerging Nonvolatile Memorys. - Shimeng Yu (Proc. IEEE, 2018)

NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning. - Pai-Yu Chen; Xiaochen Peng; Shimeng Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System. - Lixue Xia; Boxun Li; Tianqi Tang 001; Peng Gu; Pai-Yu Chen; Shimeng Yu; Yu Cao 001; Yu Wang 002; Yuan Xie 001; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design. - Rui Liu 005; Pai-Yu Chen; Xiaochen Peng; Shimeng Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Design and Analysis of Energy-Efficient and Reliable 3-D ReRAM Cross-Point Array System. - Manqing Mao; Shimeng Yu; Chaitali Chakrabarti (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis. - Wenqiang Zhang; Xiaochen Peng; Huaqiang Wu; Bin Gao 006; Hu He 001; Youhui Zhang; Shimeng Yu; He Qian (DAC, 2019)

MLP+NeuroSimV3.0: Improving On-chip Learning Performance with Device to Algorithm Optimizations. - Yandong Luo; Xiaochen Peng; Shimeng Yu (ICONS, 2019)

Evaluation of Single Event Effects in SRAM and RRAM Based Neuromorphic Computing System for Inference. - Zhilu Ye; Rui Liu 005; Hugh J. Barnaby; Shimeng Yu (IRPS, 2019)

Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory Architecture. - Xiaochen Peng; Rui Liu 005; Shimeng Yu (ISCAS, 2019)

Design Space Exploration of Ovonic Threshold Switch (OTS) for Sub-Threshold Read Operation in Cross-Point Memory Arrays. - Jiyong Woo; Shimeng Yu (ISCAS, 2019)

A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10-6 Native Bit Error Rate. - Yachun Pang; Bin Gao 006; Dong Wu; Shengyu Yi; Qi Liu 010; Wei-Hao Chen; Ting-Wei Chang; Wei-En Lin; Xiaoyu Sun 001; Shimeng Yu; He Qian; Meng-Fan Chang; et al. (ISSCC, 2019)

A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. - Xin Si; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; Yen-Cheng Chiu; Wei-Chen Wei; Ssu-Yen Wu; Xiaoyu Sun 001; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; et al. (ISSCC, 2019)

CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training. - Hongwu Jiang; Xiaochen Peng; Shanshi Huang; Shimeng Yu (MEMSYS, 2019)

Inference engine benchmarking across technological platforms from CMOS to RRAM. - Xiaochen Peng; Minkyu Kim 001; Xiaoyu Sun 001; Shihui Yin; Titash Rakshit; Ryan M. Hatcher; Jorge A. Kittl; Jae-sun Seo; Shimeng Yu (MEMSYS, 2019)

Investigating Dynamic Minor Loop of Ferroelectric Capacitor. - Panni Wang; Zheng Wang; Nujhat Tasneem; Jar Hur; Asif Islam Khan; Shimeng Yu (NVMTS, 2019)

Harnessing Intrinsic Noise in Memristor Hopfield Neural Networks for Combinatorial Optimization. - Fuxi Cai; Suhas Kumar; Thomas Van Vaerenbergh; Rui Liu 005; Can Li; Shimeng Yu; Qiangfei Xia; J. Joshua Yang; Raymond G. Beausoleil; Wei Lu 003; John Paul Strachan (CoRR, 2019)

High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS. - Shihui Yin; Xiaoyu Sun 001; Shimeng Yu; Jae-sun Seo (CoRR, 2019)

Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures. - Pai-Yu Chen; Shimeng Yu (IEEE Des. Test, 2019)

MAX2: An ReRAM-Based Neural Network Accelerator That Maximizes Data Reuse and Area Utilization. - Manqing Mao; Xiaochen Peng; Rui Liu 005; Jingtao Li; Shimeng Yu; Chaitali Chakrabarti (IEEE J. Emerg. Sel. Topics Circuits Syst., 2019)

Impact of Non-Ideal Characteristics of Resistive Synaptic Devices on Implementing Convolutional Neural Networks. - Xiaoyu Sun 001; Shimeng Yu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2019)

Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning. - Shihui Yin; Jae-sun Seo; Yulhwa Kim; Xu Han; Hugh J. Barnaby; Shimeng Yu; Yandong Luo; Wangxin He; Xiaoyu Sun 001; Jae-Joon Kim (IEEE Micro, 2019)

A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. - Xin Si; Win-San Khwa; Jia-Jing Chen; Jia-Fang Li; Xiaoyu Sun 001; Rui Liu 005; Shimeng Yu; Hiroyuki Yamauchi; Qiang Li 021; Meng-Fan Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Three-Dimensional nand Flash for Vector-Matrix Multiplication. - Panni Wang; Feng Xu; Bo Wang 067; Bin Gao 006; Huaqiang Wu; He Qian; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Impact of Selector Devices in Analog RRAM-Based Crossbar Arrays for Inference and Training of Neuromorphic System. - Jiyong Woo; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Benchmark Non-volatile and Volatile Memory Based Hybrid Precision Synapses for In-situ Deep Neural Network Training. - Yandong Luo; Shimeng Yu (ASP-DAC, 2020)

Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects. - Shimeng Yu; Xiaoyu Sun 001; Xiaochen Peng; Shanshi Huang (CICC, 2020)

A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training. - Hongwu Jiang; Shanshi Huang; Xiaochen Peng; Jian-Wei Su; Yen-Chi Chou; Wei-Hsing Huang; Ta-Wei Liu; Ruhui Liu; Meng-Fan Chang; Shimeng Yu (DAC, 2020)

Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories. - Shanshi Huang; Xiaoyu Sun 001; Xiaochen Peng; Hongwu Jiang; Shimeng Yu (DATE, 2020)

Modeling Multi-states in Ferroelectric Tunnel Junction. - Yuan-Chun Luo; Jae Hur; Panni Wang; Asif Islam Khan; Shimeng Yu (DRC, 2020)

XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption. - Shanshi Huang; Hongwu Jiang; Xiaochen Peng; Wantong Li; Shimeng Yu (ICCAD, 2020)

Impact of Read Disturb on Multilevel RRAM based Inference Engine: Experiments and Model Prediction. - Wonbo Shim; Yandong Luo; Jae-sun Seo; Shimeng Yu (IRPS, 2020)

MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture. - Hongwu Jiang; Shanshi Huang; Xiaochen Peng; Shimeng Yu (ISCAS, 2020)

A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-Out. - Yandong Luo; Xiaochen Peng; Ryan Hatcher; Titash Rakshit; Jorge Kittl; Mark S. Rodder; Jae-Sun Seo; Shimeng Yu (ISCAS, 2020)

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. - Jian-Wei Su; Xin Si; Yen-Chi Chou; Ting-Wei Chang; Wei-Hsing Huang; Yung-Ning Tu; Ruhui Liu; Pei-Jung Lu; Ta-Wei Liu; Jing-Hong Wang; Zhixiao Zhang; Hongwu Jiang; et al. (ISSCC, 2020)

Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine. - Wonbo Shim; Hongwu Jiang; Xiaochen Peng; Shimeng Yu (MEMSYS, 2020)

8T XNOR-SRAM based Parallel Compute-in-Memory for Deep Neural Network Accelerator. - Hongwu Jiang; Rui Liu 005; Shimeng Yu (MWSCAS, 2020)

Compute-in-Memory for AI: From Inference to Training. - Shimeng Yu (VLSI-DAT, 2020)

SMART Paths for Latency Reduction in ReRAM Processing-In-Memory Architecture for CNN Inference. - Sho Ko; Shimeng Yu (CoRR, 2020)

The Impact of Ferroelectric FETs on Digital and Analog Circuits and Architectures. - Xiaoming Chen 003; Kai Ni 004; Michael T. Niemier; Dayane Reis; Xiaoyu Sun 001; Panni Wang; Suman Datta; Xiaobo Sharon Hu; Xunzhao Yin; Matthew Jerry; Shimeng Yu; Ann Franchesca Laguna (IEEE Des. Test, 2020)

A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. - Xin Si; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Qiang Li 021; Meng-Fan Chang; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; et al. (IEEE J. Solid State Circuits, 2020)

CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays. - Hongwu Jiang; Xiaochen Peng; Shanshi Huang; Shimeng Yu (IEEE Trans. Computers, 2020)

Accelerating Deep Neural Network In-Situ Training With Non-Volatile and Volatile Memory Based Hybrid Precision Synapses. - Yandong Luo; Shimeng Yu (IEEE Trans. Computers, 2020)

Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures. - Xiaochen Peng; Rui Liu 005; Shimeng Yu (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint. - Anni Lu; Xiaochen Peng; Yandong Luo; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance. - Ankit Kaul; Yandong Luo; Xiaochen Peng; Shimeng Yu; Muhannad S. Bakir (3DIC, 2021)

NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro. - Anni Lu; Xiaochen Peng; Wantong Li; Hongwu Jiang; Shimeng Yu (AICAS, 2021)

Compute-in-RRAM with Limited On-chip Resources. - Anni Lu; Xiaochen Peng; Shimeng Yu (AICAS, 2021)

Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security. - Wantong Li; Shanshi Huang; Xiaoyu Sun 001; Hongwu Jiang; Shimeng Yu (CICC, 2021)

A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator. - Anni Lu; Xiaochen Peng; Yandong Luo; Shanshi Huang; Shimeng Yu (DATE, 2021)

A FeRAM based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Training. - Yandong Luo; Yuan-Chun Luo; Shimeng Yu (DATE, 2021)

Experimental RF Characterization of Ferroelectric Hafnium Zirconium Oxide Material at GHz for Microwave Applications. - Boce Lin; Gihun Choe; Jae Hur; Asif Islam Khan; Shimeng Yu; Hua Wang 006 (DRC, 2021)

A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References. - Wantong Li; Xiaoyu Sun 001; Hongwu Jiang; Shanshi Huang; Shimeng Yu (ESSDERC, 2021)

Compute-in-Memory: From Device Innovation to 3D System Integration. - Shimeng Yu; Wonbo Shim; Jae Hur; Yuan-chun Luo; Gihun Choe; Wantong Li; Anni Lu; Xiaochen Peng (ESSDERC, 2021)

A Technology Path for Scaling Embedded FeRAM to 28nm with 2T1C Structure. - Jae Hur; Yuan-Chun Luo; Zheng Wang; Wonbo Shim; Asif Islam Khan; Shimeng Yu (IMW, 2021)

Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing. - Yuan-Chun Luo; Anni Lu; Jae Hur; Shaolan Li; Shimeng Yu (IMW, 2021)

Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing. - Wangxin He; Wonbo Shim; Shihui Yin; Xiaoyu Sun 001; Deliang Fan; Shimeng Yu; Jae-sun Seo (IRPS, 2021)

Impact of Multilevel Retention Characteristics on RRAM based DNN Inference Engine. - Wonbo Shim; Jian Meng; Xiaochen Peng; Jae-sun Seo; Shimeng Yu (IRPS, 2021)

Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning. - Shanshi Huang; Xiaochen Peng; Hongwu Jiang; Yandong Luo; Shimeng Yu (ISCAS, 2021)

Cryogenic Performance for Compute-in-Memory Based Deep Neural Network Accelerator. - Panni Wang; Xiaochen Peng; Wriddhi Chakraborty; Asif Khan; Suman Datta; Shimeng Yu (ISCAS, 2021)

Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune. - Shanshi Huang; Hongwu Jiang; Shimeng Yu (NVMSA, 2021)

Genetic Algorithm-Based Energy-Aware CNN Quantization for Processing-In-Memory Architecture. - Beomseok Kang; Anni Lu; Yun Long; Daehyun Kim 002; Shimeng Yu; Saibal Mukhopadhyay (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark. - Anni Lu; Xiaochen Peng; Wantong Li; Hongwu Jiang; Shimeng Yu (Frontiers Artif. Intell., 2021)

A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source. - Bohan Lin; Yachuan Pang; Bin Gao 006; Jianshi Tang; Dong Wu; Ting-Wei Chang; Wei-En Lin; Xiaoyu Sun 001; Shimeng Yu; Meng-Fan Chang; He Qian; Huaqiang Wu (IEEE J. Solid State Circuits, 2021)

A wearable sensor vest for social humanoid robots with GPGPU, IoT, and modular software architecture. - Mohsen Jafarzadeh; Stephen Brooks; Shimeng Yu; Balakrishnan Prabhakaran 001; Yonas Tadesse (Robotics Auton. Syst., 2021)

AILC: Accelerate On-Chip Incremental Learning With Compute-in-Memory Technology. - Yandong Luo; Shimeng Yu (IEEE Trans. Computers, 2021)

DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training. - Xiaochen Peng; Shanshi Huang; Hongwu Jiang; Anni Lu; Shimeng Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

RRAM for Compute-in-Memory: From Inference to Training. - Shimeng Yu; Wonbo Shim; Xiaochen Peng; Yandong Luo (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks. - Jian Meng; Li Yang 009; Xiaochen Peng; Shimeng Yu; Deliang Fan; Jae-Sun Seo (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning Inference. - Anni Lu; Xiaochen Peng; Yandong Luo; Shanshi Huang; Shimeng Yu (ACM Trans. Design Autom. Electr. Syst., 2021)

Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption. - Shanshi Huang; Hongwu Jiang; Xiaochen Peng; Wantong Li; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM. - Gauthaman Murali; Xiaoyu Sun 001; Shimeng Yu; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Temporal Frame Filtering with Near-Pixel Compute for Autonomous Driving. - Wantong Li; Qiucheng Wu; Janak Sharda; Shiyu Chang; Shimeng Yu (AICAS, 2022)

Design-Technology Co-optimization for Cryogenic Tensor Processing Unit. - Dong Suk Kang; Shimeng Yu (APCCAS, 2022)

Improved Endurance with Electron-Only Switching in Ferroelectric Devices. - Zheng Wang; Nujhat Tasneem; Hang Chen; Shimeng Yu; Winston Chern; Asif Islam Khan (DRC, 2022)

A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling. - Wantong Li; James Read; Hongwu Jiang; Shimeng Yu (ESSCIRC, 2022)

In-Memory 3D NAND Flash Hyperdimensional Computing Engine for Energy-Efficient SARS-CoV-2 Genome Sequencing. - Po-Kai Hsu; Shimeng Yu (IMW, 2022)

Performance Benchmarking of Spin-Orbit Torque Magnetic RAM (SOT-MRAM) for Deep Neural Network (DNN) Accelerators. - Yandong Luo; Piyush Kumar; Yu-Ching Liao; William Hwang; Fen Xue; Wilman Tsai; Shan X. Wang; Azad Naeemi; Shimeng Yu (IMW, 2022)

Sparse and Robust RRAM-based Efficient In-memory Computing for DNN Inference. - Jian Meng; Injune Yeo; Wonbo Shim; Li Yang 009; Deliang Fan; Shimeng Yu; Jae-Sun Seo (IRPS, 2022)

A Method for Reverse Engineering Neural Network Parameters from Compute-in-Memory Accelerators. - James Read; Wantong Li; Shimeng Yu (ISVLSI, 2022)

A monolithic 3D design technology co-optimization with back-end-of-line oxide channel transistor. - Jungyoun Kwak; Gihun Choe; Shimeng Yu (NANOARCH, 2022)

A Thousand State Superlattice(SL) FEFET Analog Weight Cell. - Khandker Akif Aabrar; Sharadindu Gopal Kirtania; A. Lu; A. Khanna; Wriddhi Chakraborty; M. San Jose; Shimeng Yu; Suman Datta (VLSI Technology and Circuits, 2022)

Machine Learning Assisted Statistical Variation Analysis of Ferroelectric Transistors: From Experimental Metrology to Predictive Modeling. - Gihun Choe; Prasanna Venkatesan Ravindran; Anni Lu; Jae Hur; Maximilian Lederer; André Reck; Sarah Lombardo; Nashrah Afroze; Josh Kacher; Asif Islam Khan; Shimeng Yu (VLSI Technology and Circuits, 2022)

A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays. - Hongwu Jiang; Wantong Li; Shanshi Huang; Shimeng Yu (VLSI Technology and Circuits, 2022)

BEOL Compatible Ferroelectric Routers for Run-time Reconfigurable Compute-in-Memory Accelerators. - Abhishek Khanna; Huacheng Ye; Y. Luo; G. Bajpai; M. San Jose; Wriddhi Chakraborty; Shimeng Yu; Patrick Fay; Suman Datta (VLSI Technology and Circuits, 2022)

Determination of Domain Wall Velocity and Nucleation Time by Switching Dynamics Studies of Ferroelectric Hafnium Zirconium Oxide. - Xiao Lyu; Pragya R. Shrestha; Mengwei Si; Panni Wang; Junkang Li; Kin P. Cheung; Shimeng Yu; Peide D. Ye (VLSI Technology and Circuits, 2022)

Nonvolatile Capacitive Crossbar Array for In-Memory Computing. - Jae Hur; Yuan-Chun Luo; Anni Lu; Tzu-Han Wang; Shaolan Li; Asif Islam Khan; Shimeng Yu (Adv. Intell. Syst., 2022)

Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators. - Hongwu Jiang; Wantong Li; Shanshi Huang; Stefan Cosemans; Francky Catthoor; Shimeng Yu (IEEE Des. Test, 2022)

MAC-ECC: In-Situ Error Correction and Its Design Methodology for Reliable NVM-Based Compute-in-Memory Inference Engine. - Wantong Li; James Read; Hongwu Jiang; Shimeng Yu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect. - Yandong Luo; Sourav Dutta; Ankit Kaul; Sung Kyu Lim; Muhannad S. Bakir; Suman Datta; Shimeng Yu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

GP3D: 3D NAND Based In-Memory Graph Processing Accelerator. - Wonbo Shim; Shimeng Yu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Guest Editorial Memristive Circuits and Systems for Edge-Computing Applications. - Georgios Ch. Sirakoulis; Alon Ascoli; Ronald Tetzlaff; Shimeng Yu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Accelerating On-Chip Training with Ferroelectric-Based Hybrid Precision Synapse. - Yandong Luo; Panni Wang; Shimeng Yu (ACM J. Emerg. Technol. Comput. Syst., 2022)

A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References. - Wantong Li; Xiaoyu Sun 001; Shanshi Huang; Hongwu Jiang; Shimeng Yu (IEEE J. Solid State Circuits, 2022)

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips. - Jian-Wei Su; Xin Si; Yen-Chi Chou; Ting-Wei Chang; Wei-Hsing Huang; Yung-Ning Tu; Ruhui Liu; Pei-Jung Lu; Ta-Wei Liu; Jing-Hong Wang; Yen-Lin Chung; Jin-Sheng Ren; et al. (IEEE J. Solid State Circuits, 2022)

Temperature-Resilient RRAM-Based In-Memory Computing for DNN Inference. - Jian Meng; Wonbo Shim; Li Yang 009; Injune Yeo; Deliang Fan; Shimeng Yu; Jae-sun Seo (IEEE Micro, 2022)

A Ferroelectric-Based Volatile/Non-Volatile Dual-Mode Buffer Memory for Deep Neural Network Accelerators. - Yandong Luo; Yuan-Chun Luo; Shimeng Yu (IEEE Trans. Computers, 2022)

Robust Processing-In-Memory With Multibit ReRAM Using Hessian-Driven Mixed-Precision Computation. - Saurabh Dash; Yandong Luo; Anni Lu; Shimeng Yu; Saibal Mukhopadhyay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing. - Yuan-Chun Luo; Anni Lu; Jae Hur; Shaolan Li; Shimeng Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices. - Shanshi Huang; Xiaoyu Sun 001; Xiaochen Peng; Hongwu Jiang; Shimeng Yu (ACM Trans. Design Autom. Electr. Syst., 2022)

Optimization Strategies for Digital Compute-in-Memory from Comparative Analysis with Systolic Array. - Wantong Li; Junmo Lee; Shimeng Yu (AICAS, 2023)

Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator. - Wantong Li; Xitie Zhang; Junmo Lee; F. Levent Degertekin; Shaolan Li; Shimeng Yu (BioCAS, 2023)

PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration. - Wangxin He; Jian Meng; Sujan Kumar Gonugondla; Shimeng Yu; Naresh R. Shanbhag; Jae-sun Seo (DATE, 2023)

RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers. - Wantong Li; Yandong Luo; Shimeng Yu (DATE, 2023)

CLUE: Cross-Layer Uncertainty Estimator for Reliable Neural Perception using Processing-in-Memory Accelerators. - Minah Lee; Anni Lu; Mandovi Mukherjee; Shimeng Yu; Saibal Mukhopadhyay (IJCNN, 2023)

Design of Ferroelectric-Metal Field-Effect Transistor for Multi-Level-Cell 3D NAND Flash. - Sola Woo; Gihun Choe; Asif Islam Khan; Suman Datta; Shimeng Yu (IMW, 2023)

Low-Frequency Noise Characteristics of Ferroelectric Field-Effect Transistors. - Omkar Phadke; Khandker Akif Aabrar; Yuan-chun Luo; Sharadindu Gopal Kirtania; Asif Islam Khan; Suman Datta; Shimeng Yu (IRPS, 2023)

Enabling Long-Term Robustness in RRAM-based Compute-In-Memory Edge Devices. - James Read; Wantong Li; Shimeng Yu (ISCAS, 2023)

An In-Storage Processing Architecture with 3D NAND Heterogeneous Integration for Spectra Open Modification Search. - Po-Kai Hsu; Weihong Xu; Tajana Rosing; Shimeng Yu (MEMSYS, 2023)

A Reconfigurable Monolithic 3D Switched-Capacitor DC-DC Converter with Back-End-of-Line Oxide Channel Transistor. - Jungyoun Kwak; Wantong Li; Shimeng Yu (MWSCAS, 2023)

Cold-FeFET as Embedded Non-Volatile Memory with Unlimited Cycling Endurance. - Sharadindu Gopal Kirtania; Khandker Akif Aabrar; Asif Islam Khan; Shimeng Yu; Samyak Datta (VLSI Technology and Circuits, 2023)

Proxima: Near-storage Acceleration for Graph-based Approximate Nearest Neighbor Search in 3D NAND. - Weihong Xu; Junwei Chen; Po-Kai Hsu; Jaeyoung Kang 001; Minxuan Zhou; Sumukh Pinge; Shimeng Yu; Tajana Rosing (CoRR, 2023)

Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators. - Shanshi Huang; Hongwu Jiang; Shimeng Yu (ACM Trans. Design Autom. Electr. Syst., 2023)

ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays. - Hongwu Jiang; Shanshi Huang; Wantong Li; Shimeng Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Scalable In-Memory Clustered Annealer With Temporal Noise of Charge Trap Transistor for Large Scale Travelling Salesman Problems. - Anni Lu; Jae Hur; Yuan-Chun Luo; Hai Li 008; Dmitri E. Nikonov; Ian A. Young; Yang-Kyu Choi; Shimeng Yu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Temporal Frame Filtering for Autonomous Driving Using 3D-Stacked Global Shutter CIS With IWO Buffer Memory and Near-Pixel Compute. - Janak Sharda; Wantong Li; Qiucheng Wu; Shiyu Chang; Shimeng Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention. - Wantong Li; Madison Manley; James Read; Ankit Kaul; Muhannad S. Bakir; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Accelerator Design using 3D Stacked Capacitorless DRAM for Large Language Models. - Janak Sharda; Po-Kai Hsu; Shimeng Yu (AICAS, 2024)

3D Digital Compute-in-Memory Benchmark with A5 CFET Technology. - Minji Shon; Junmo Lee; Shimeng Yu (APCCAS, 2024)

A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory Accelerators. - Yuan-Chun Luo; James Read; Anni Lu; Shimeng Yu (ASPDAC, 2024)

Digital CIM with Noisy SRAM Bit: A Compact Clustered Annealer for Large-Scale Combinatorial Optimization. - Anni Lu; Junmo Lee; Yuan-Chun Luo; Hai Li 008; Ian A. Young; Shimeng Yu (DAC, 2024)

Optimization of Backside of Silicon-Compatible High Voltage Superlattice Capacitor for 12V-to-6V On-Chip Voltage Conversion. - Junmo Lee; Sunbin Deng; Jungyoun Kwak; Minji Shon; Suman Datta; Shimeng Yu (DRC, 2024)

Design Framework for Ferroelectric Gate Stack Engineering of Vertical NAND Structures for Efficient TLC and QLC Operation. - Dipjyoti Das; Lance Fernandes; Prasanna Venkatesan Ravindran; Taeyoung Song; Chinsung Park; Nashrah Afroze; Mengkun Tian; Hang Chen; Winston Chem; Kijoon Kim; Jongho Woo; Suhwan Lim; et al. (IMW, 2024)

Engineering nvCap From FEOL to BEOL with Ferroelectric Small-signal Non-destructive Read. - Tae-Hyeon Kim; Yuan-Chun Luo; Omkar Phadke; James Read; Shimeng Yu (IMW, 2024)

Reliability Assesement of Ferroelectric nvCAP for Small-Signal Capacitive Read-Out. - Omkar Phadke; Halid Mulaosmanovic; Stefan Dünkel; Sven Beyer; Shimeng Yu (IRPS, 2024)

Comprehensive Time Dependent Dielectric Breakdown (TDDB) Characterization of Ferroelectric Capacitors Under Bipolar Stress Conditions. - Priyankka Gundlapudi Ravikumar; Prasanna Venkatesan Ravindran; Khandker Akif Aabrar; Taeyoung Song; Sharadindu Gopal Kirtania; Dipjyoti Das; Chinsung Park; Nashrah Afroze; Mengkun Tian; Shimeng Yu; Ahmad Ehtesham Islam; Suman Datta; et al. (IRPS, 2024)

Monolithic 3D Transposable 3T Embedded DRAM with Back-end-of-line Oxide Channel Transistor. - Jungyoun Kwak; Gihun Choe; Junmo Lee; Shimeng Yu (ISCAS, 2024)

A Reconfigurable Bandpass Filter with Ferroelectric Devices for Intracardiac Electrograms Monitoring. - Jianwei Jia; Zhenge Jia; Omkar Phadke; Gihun Choe; Yiyu Shi 001; Shimeng Yu (MWSCAS, 2024)

Impact of In-Pixel Processing Circuit Non-idealities on Multi-object Tracking Accuracy for Autonomous Driving. - Janak Sharda; Qiucheng Wu; Shiyu Chang; Shimeng Yu (MWSCAS, 2024)

Amorphous Oxide Semiconductors for Monolithic 3D Integrated Circuits. - Suman Datta; Eknath Sarkar; Khandker Akif Aabrar; Shan Deng; Jaewon Shin; Arijit Raychowdhury; Shimeng Yu; Asif Khan (VLSI Technology and Circuits, 2024)

Demonstration of On-Chip Switched-Capacitor DC-DC Converters using BEOL Compatible Oxide Power Transistors and Superlattice MIM Capacitors. - Sunbin Deng; Jungyoun Kwak; Junmo Lee; Dyutimoy Chakraborty; Jaewon Shin; Omkar Phadke; Sharadindu Gopal Kirtania; Chengyang Zhang; Khandker Akif Aabrar; Shimeng Yu; Suman Datta (VLSI Technology and Circuits, 2024)

Co-Optimization for Robust Power Delivery Design in 3D-Heterogeneous Integration of Compute In-Memory Accelerators. - Ankit Kaul; Madison Manley; James Read; Yandong Luo; Xiaochen Peng; Shimeng Yu; Muhannad S. Bakir (VLSI Technology and Circuits, 2024)

Back-side Design Methodology for Power Delivery Network and Clock Routing. - Pruek Vanna-Iampikul; Hang Yang; Jungyoun Kwak; Joyce X. Hu; Amaan Rahman; Nesara Eranna Bethur; Callie Hao; Shimeng Yu; Sung Kyu Lim (VLSI Technology and Circuits, 2024)

P-type SnO Semiconductor Transistor and Application. - C. C. Wang; C. C. Kuo; C. H. Wu; A. Lu; H. Y. Lee; C. F. Hsu; P. J. Tzeng; T. Y. Lee; F. R. Hou; M. H. Chang; S. C. Lai; K. Goto; et al. (VLSI Technology and Circuits, 2024)

Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate. - Zijian Zhao 001; Sola Woo; Khandker Akif Aabrar; Sharadindu Gopal Kirtania; Zhouhang Jiang; Shan Deng; Yi Xiao 008; Halid Mulaosmanovic; Stefan Dünkel; Dominik Kleimaier; Steven Soss; Sven Beyer; et al. (CoRR, 2024)

Towards Reverse-Engineering the Brain: Brain-Derived Neuromorphic Computing Approach with Photonic, Electronic, and Ionic Dynamicity in 3D integrated circuits. - S. J. Ben Yoo; Luis El Srouji; Suman Datta; Shimeng Yu; Jean Anne C. Incorvia; Alberto Salleo; Volker J. Sorger; Juejun Hu; Lionel C. Kimerling; Kristofer Bouchard; Joy Geng; Rishidev Chaudhuri; et al. (CoRR, 2024)

A FeFET-Based ADC Offset Robust Compute-In-Memory Architecture for Streaming Keyword Spotting (KWS). - Yandong Luo; Johan Vanderhaegen; Oleg Rybakov; Martin Kraemer; Niel Warren; Shimeng Yu (IEEE Trans. Emerg. Top. Comput., 2024)

Neuro-Symbolic Computing: Advancements and Challenges in Hardware-Software Co-Design. - Xiaoxuan Yang 001; Zhangyang Wang; X. Sharon Hu; Chris H. Kim; Shimeng Yu; Miroslav Pajic; Rajit Manohar; Yiran Chen 001; Hai Helen Li (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Semiconductor Memory Technologies: State-of-the-Art and Future Trends. - Shimeng Yu; Tae-Hyeon Kim (Computer, 2024)

A Heterogeneous Platform for 3D NAND-Based In-Memory Hyperdimensional Computing Engine for Genome Sequencing Applications. - Po-Kai Hsu; Vaidehi Garg; Anni Lu; Shimeng Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

NeuroSim V1.4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node. - Junmo Lee; Anni Lu; Wantong Li; Shimeng Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

H3D-Transformer: A Heterogeneous 3D (H3D) Computing Platform for Transformer Model Acceleration on Edge Devices. - Yandong Luo; Shimeng Yu (ACM Trans. Design Autom. Electr. Syst., 2024)

Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture. - Yuan-Chun Luo; Anni Lu; Yandong Luo; Sou-Chi Chang; Uygar Avci; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads. - Yuan-Chun Luo; Anni Lu; Janak Sharda; Moritz Scherer 001; Jorge Tomás Gómez; Syed Shakib Sarwar; Ziyun Li; Reid Frederick Pinkham; Barbara De Salvo; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference. - Wei-Hsing Huang; Jianwei Jia; Yuyao Kong; Faaiq G. Waqar; Tai-Hao Wen; Meng-Fan Chang; Shimeng Yu (ASP-DAC, 2025)

Runtime Security Analysis of Monolithic 3D Embedded DRAM with Oxide-Channel Transistor. - Eduardo Ortega; Jungyoun Kwak; Shimeng Yu; Krishnendu Chakrabarty (DATE, 2025)

Comparative Study of Channel Materials for Ferroelectric NAND Applications. - Lance Fernandes; Prasanna Venkatesan Ravindran; Mengkun Tian; Yu-Hsin Kuo; Nashrah Afroze; Salma Soliman; Sanghyun Kang; Dyutimoy Chakraborty; Taeyoung Song; Chengyang Zhang; Kijoon Kim; Kwangyou Seo; et al. (IMW, 2025)

Monolithic 3D Stackable DRAM Design with BEOL-Compatible Oxide Channel Access Transistor. - Po-Kai Hsu; Sungwon Cho; Janak Sharda; Hyeonwoo Park; Suman Datta; Shimeng Yu (IMW, 2025)

Analog In-Memory-Compute with Multi-bit Silicon Ferro FinFET Array for Improved Energy and Area Efficiency. - Eknath Sarkar; Dyutimoy Chakraborty; Wei-Chun Wang; Khandker Akif Aabrar; Sharadindu Gopal Kirtania; Omkar Phadke; Chengyang Zhang; Emmanuel Quezada; Jaewon Shin; Shida Zhang; Asif Islam Khan; Shimeng Yu; et al. (IMW, 2025)

Radiation-Resilient Amorphous Indium Oxide FEFETs for Embedded Nonvolatile Memory. - Sharadindu Gopal Kirtania; Faaiq G. Waqar; Dyutimoy Chakraborty; Jaewon Shin; Eknath Sarkar; Justin Reiss; Jason Dean Yeager; Douglas E. Wolfe; Shimeng Yu; Suman Datta (IRPS, 2025)

Machine Learning-Assisted Modeling of AC Stress-Induced Bias Temperature Instability in Oxide Channel Transistors for 2T Gain Cell eDRAM. - Jungyoun Kwak; Chengyang Zhang; Gyujun Jeong; Omkar Phadke; Sharadindu Gopal Kirtania; Junmo Lee; Suman Datta; Shimeng Yu (IRPS, 2025)

Understanding Correlation Between Memory Window Closure, Leakage and Read Delay Effects for FEFET Reliability Improvement: Role of IL and FE Traps. - Priyankka Gundlapudi Ravikumar; Andrea Padovani; Prasanna Venkatesan Ravindran; Chinsung Park; Nashrah Afroze; Mengkun Tian; Suman Datta; Shimeng Yu; Luca Larcher; Gaurav Thareja; Asif Khan (IRPS, 2025)

Enhanced Memory Performance in Ferroelectric NAND Applications: The Role of Tunnel Dielectric Position for Robust 10-Year Retention. - Prasanna Venkatesan Ravindran; Andrea Padovani; Lance Fernandes; Priyankka Gundlapudi Ravikumar; Chinsung Park; Huy Tran; Zekai Wang; Hari Jayasankar; Amrit Garlapati; Taeyoung Song; Hang Chen; Winston Chern; et al. (IRPS, 2025)

Modeling Dynamic Interplay Between Charge Traps and Polarization for Memory Window Enhancement in Gate Injection Layers. - Minji Shon; Chinsung Park; Prasanna Venkatesan Ravindran; Lance Fernandes; Kijoon Kim; Jongho Woo; Suhwan Lim; Kwangsoo Kim; Wanki Kim; Daewon Ha; Suman Datta; Asif Khan; et al. (IRPS, 2025)

Digital Compute-in-Memory Ising Annealer with Ferroelectric Capacitor-Based nvSRAM for Combinatorial Optimization Problems. - Yuyao Kong; Jianwei Jia; Anni Lu; Faaiq G. Waqar; Yuan-Chun Luo; Hai Li 001; Ian A. Young; Shimeng Yu (ISCAS, 2025)

Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories. - Faaiq G. Waqar; Jiahao Zhang; Anni Lu; Zifan He; Jason Cong; Shimeng Yu (CoRR, 2025)

Capacitive Synaptor with Gate Surrounding Semiconductor Pillar Structure and Overturned Charge Injection for Compute-in-Memory. - Choong-Ki Kim; James Read; Minji Shon; Tae-Hyeon Kim; Myung-Su Kim; Ji-Man Yu; Min-Soo Yoo; Yang-Kyu Choi; Shimeng Yu (Adv. Intell. Syst., 2025)

Optimization and Benchmarking of Monolithically Stackable Gain Cell Memory for Last-Level Cache. - Faaiq G. Waqar; Jungyoun Kwak; Junmo Lee; Minji Shon; MohammadHosein Gholamrezaei; Kevin Skadron; Shimeng Yu (CoRR, 2025)

An In-Situ Spatial-Temporal Sequence Detector for Neuromorphic Vision Sensor Empowered by High Density Vertical NAND Storage. - Zijian Zhao 001; Varun Darshana Parekh; Po-Kai Hsu; Yixin Qin; Yiming Song; A. N. M. Nafiul Islam; Ningyuan Cao; Siddharth Joshi 001; Thomas Kämpfe; Moonyoung Jung; Kwangyou Seo; Kwangsoo Kim; et al. (CoRR, 2025)

NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities. - James Read; Ming-Yen Lee; Wei-Hsing Huang; Yuan-Chun Luo; Anni Lu; Shimeng Yu (CoRR, 2025)

CMOS+X: Stacking Persistent Embedded Memories based on Oxide Transistors upon GPGPU Platforms. - Faaiq Waqar; Ming-Yen Lee; Seongwon Yoon; Seongkwang Lim; Shimeng Yu (CoRR, 2025)

SLIM: A Heterogeneous Accelerator for Edge Inference of Sparse Large Language Model via Adaptive Thresholding. - Weihong Xu; Haein Choi; Po-Kai Hsu; Shimeng Yu; Tajana Rosing (CoRR, 2025)

3DGauCIM: Accelerating Static/Dynamic 3D Gaussian Splatting via Digital CIM for High Frame Rate Real-Time Edge Rendering. - Wei-Hsing Huang; Cheng-Jhih Shih; Jian-Wei Su; Samuel Wade Wang; Vaidehi Garg; Yuyao Kong; Jen-Chun Tien; Nealson Li; Arijit Raychowdhury; Meng-Fan Chang; Yingyan Lin; Shimeng Yu (CoRR, 2025)

A3D-MoE: Acceleration of Large Language Models with Mixture of Experts via 3D Heterogeneous Integration. - Wei-Hsing Huang; Janak Sharda; Cheng-Jhih Shih; Yuyao Kong; Faaiq Waqar; Pin-Jun Chen; Yingyan Lin; Shimeng Yu (CoRR, 2025)

3-D Digital Compute-in-Memory Benchmark With A5 CFET Technology: An Extension to Lookup-Table-Based Design. - Junmo Lee; Minji Shon; Faaiq G. Waqar; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Architecting Long-Context LLM Acceleration with Packing-Prefetch Scheduler and Ultra-Large Capacity On-Chip Memories. - Ming-Yen Lee; Faaiq Waqar; Hanchen Yang; Muhammed Ahosan Ul Karim; Harsono Simka; Shimeng Yu (CoRR, 2025)

Backside Active Power Delivery With Hybrid DC-DC Converter Enabled by Amorphous Oxide Semiconductor Transistors. - Jungyoun Kwak; Sunbin Deng; Junmo Lee; Suman Datta; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2025)