A Study of an Infrastructure for Research and Development of Many-Core Processors. - Koh Uehara; Shimpei Sato; Takefumi Miyoshi; Kenji Kise (PDCAT, 2009)

SimCell: A Processor Simulator for Multi-Core Architecture Research. - Shimpei Sato; Naoki Fujieda; Akira Moriya; Kenji Kise (Inf. Media Technol., 2009)

Pattern-Based Systematic Task Mapping for Many-Core Processors. - Shintaro Sano; Masahiro Sano; Shimpei Sato; Takefumi Miyoshi; Kenji Kise (ICNC, 2010)

Smart Core System for Dependable Many-Core Processor with Multifunction Routers. - Shinya Takamaeda; Shimpei Sato; Takefumi Miyoshi; Kenji Kise (ICNC, 2010)

The Ultrasmall soft processor. - Yuichiro Tanaka; Shimpei Sato; Kenji Kise (SIGARCH Comput. Archit. News, 2013)

KNoCEmu: High Speed FPGA Emulator for Kilo-node Scale NoCs. - Thiem Van Chu; Shimpei Sato; Kenji Kise (MCSoC, 2014)

ArchHDL: A Novel Hardware RTL Design Environment in C++. - Shimpei Sato; Kenji Kise (ARC, 2015)

Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA. - Thiem Van Chu; Shimpei Sato; Kenji Kise (FCCM, 2015)

Ultra-fast NoC emulation on a single FPGA. - Thiem Van Chu; Shimpei Sato; Kenji Kise (FPL, 2015)

Effective Parallel Simulation of ArchHDL under Manycore Environment. - Tomohiro Misono; Ryohei Kobayashi 001; Shimpei Sato; Kenji Kise (CANDAR, 2015)

Exana: an execution-driven application analysis tool for assisting productive performance tuning. - Yukinori Sato; Shimpei Sato; Toshio Endo (SEPS@SPLASH, 2015)

Investigating potential performance benefits of memory layout optimization based on roofline model. - Shimpei Sato; Yukinori Sato; Toshio Endo (SEPS@SPLASH, 2015)

A fully connected layer elimination for a binarizec convolutional neural network on an FPGA. - Hiroki Nakahara; Tomoya Fujii; Shimpei Sato (FPL, 2017)

An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA. - Hiroki Nakahara; Haruyoshi Yonekawa; Shimpei Sato (FPT, 2017)

All binarized convolutional neural network and its implementation on an FPGA. - Masayuki Shimoda; Shimpei Sato; Hiroki Nakahara (FPT, 2017)

In-memory area-efficient signal streaming processor design for binary neural networks. - Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Kota Ando; Kodai Ueyoshi; Kazutoshi Hirose; Kentaro Orimo; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (MWSCAS, 2017)

Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA. - Thiem Van Chu; Shimpei Sato; Kenji Kise (ACM Trans. Reconfigurable Technol. Syst., 2017)

A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA. - Hiroki Nakahara; Haruyoshi Yonekawa; Tomoya Fujii; Shimpei Sato (FPGA, 2018)

A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2). - Hiroki Nakahara; Masayuki Shimoda; Shimpei Sato (FPL, 2018)

Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs. - Masayuki Shimoda; Shimpei Sato; Hiroki Nakahara (FPL, 2018)

An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural Network. - Akira Jinguji; Tomoya Fujii; Shimpei Sato; Hiroki Nakahara (FPT, 2018)

A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector. - Hiroki Nakahara; Masayuki Shimoda; Shimpei Sato (FPT, 2018)

A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS). - Haoxuan Cheng; Shimpei Sato; Hiroki Nakahara (HEART, 2018)

Power Efficient Object Detector with an Event-Driven Camera on an FPGA. - Masayuki Shimoda; Shimpei Sato; Hiroki Nakahara (HEART, 2018)

A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor. - Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara (ISMVL, 2018)

Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses. - Atsushi Takahashi 001; Shimpei Sato; Hiroki Ogura; Yu-Min Sung; Ting-Chi Wang (ISVLSI, 2018)

A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA. - Tomoya Fujii; Shimpei Sato; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2018)

An FPGA Realization of a Random Forest with k-Means Clustering Using a High-Level Synthesis Design. - Akira Jinguji; Shimpei Sato; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2018)

ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment. - Shimpei Sato; Ryohei Kobayashi 001; Kenji Kise (IEICE Trans. Inf. Syst., 2018)

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. - Kota Ando; Kodai Ueyoshi; Kentaro Orimo; Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Tadahiro Kuroda; Masato Motomura (IEEE J. Solid State Circuits, 2018)

An FPGA-based Fine Tuning Accelerator for a Sparse CNN. - Hiroki Nakahara; Akira Jinguji; Masayuki Shimoda; Shimpei Sato (FPGA, 2019)

FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network. - Hiroki Nakahara; Youki Sada; Masayuki Shimoda; Kouki Sayama; Akira Jinguji; Shimpei Sato (FPL, 2019)

A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution. - Shimpei Sato; Eijiro Sassa; Yuta Ukon; Atsushi Takahashi 001 (ISCAS, 2019)

Noise Convolutional Neural Networks and FPGA Implementation. - Atsuki Munakata; Hiroki Nakahara; Shimpei Sato (ISMVL, 2019)

Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks. - Ryosuke Kuramochi; Youki Sada; Masayuki Shimoda; Shimpei Sato; Hiroki Nakahara (MCSoC, 2019)

FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System. - Ryosuke Kuramochi; Masayuki Shimoda; Youki Sada; Shimpei Sato; Hiroki Nakahara (ReConFig, 2019)

GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers. - Hiroki Nakahara; Haruyoshi Yonekawa; Tomoya Fujii; Masayuki Shimoda; Shimpei Sato (IEICE Trans. Inf. Syst., 2019)

A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution. - Shimpei Sato; Eijiro Sassa; Yuta Ukon; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA. - Masayuki Shimoda; Shimpei Sato; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2019)

Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs. - Akira Jinguji; Shimpei Sato; Hiroki Nakahara (FCCM, 2020)

Fast Monocular Depth Estimation on an FPGA. - Youki Sada; Naoto Soga; Masayuki Shimoda; Akira Jinguji; Shimpei Sato; Hiroki Nakahara (IPDPS Workshops, 2020)

A Table Look-Up Based Ternary Neural Network Processor. - Yuta Suzuki; Naoto Soga; Shimpei Sato; Hiroki Nakahara (ISMVL, 2020)

A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections. - Shimpei Sato; Kano Akagi; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)

SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators. - Masayuki Shimoda; Youki Sada; Ryosuke Kuramochi; Shimpei Sato; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2020)

Drop Prevention Control for Humanoid Robots Carrying Stacked Boxes. - Shimpei Sato; Yuta Kojio; Kunio Kojima; Fumihito Sugai; Yohei Kakiuchi; Kei Okada; Masayuki Inaba (IROS, 2021)

Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs. - Akira Jinguji; Shimpei Sato; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2021)

Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder. - Naoto Soga; Shimpei Sato; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2021)

Trajectory Generation and Compensation for External Forces with a Leg-wheeled Robot Designed for Human Passengers. - Yohei Kakiuchi; Yuta Kojio; Noriaki Imaoka; Daiki Kusuyama; Shimpei Sato; Yutaro Matsuura; Takeshi Ando; Masayuki Inaba (Humanoids, 2022)

Robust Humanoid Walking System Considering Recognized Terrain and Robots' Balance. - Shimpei Sato; Yuta Kojio; Yohei Kakiuchi; Kunio Kojima; Kei Okada; Masayuki Inaba (IROS, 2022)

Whole-Body Torque Control Without Joint Position Control Using Vibration-Suppressed Friction Compensation for Bipedal Locomotion of Gear-Driven Torque Sensorless Humanoid. - Takuma Hiraoka; Shimpei Sato; Naoki Hiraoka; Annan Tang; Kunio Kojima; Kei Okada; Masayuki Inaba; Koji Kawasaki (IROS, 2023)

Humanoid Walking System with CNN-Based Uneven Terrain Recognition and Landing Control with Swing-Leg Velocity Constraints. - Shimpei Sato; Kunio Kojima; Naoki Hiraoka; Kei Okada; Masayuki Inaba (IROS, 2023)

On Relation Between Leakage-Free Condition and Differential Filtering Order in ETFE-Based Frequency Responce Function Estimation*. - Yoshihiro Maeda; Taishi Yazawa; Shimpei Sato; Wataru Hara (AIM, 2024)

Direct Data-Driven Control-Based Additive Feedforward Compensation for Fast and Precise Positioning Control. - Daigo Yamaguchi; Shimpei Sato; Yoshihiro Maeda (AIM, 2024)

Data-Driven Feedforward Control for Suppressing Coupled Vibrations in Positioning Systems. - Shota Teramoto; Daigo Yamaguchi; Shimpei Sato; Yoshihiro Maeda (ICM, 2025)

Application of 9-Channel Pseudo-Color Maps in Deep Learning for Intracranial Hemorrhage Detection. - Shimpei Sato; Daisuke Oura; Hiroyuki Sugimori (Multimodal Technol. Interact., 2025)