A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS. - Yong-Un Jeong; Joo-Hyung Chae; Sungphil Choi; Jaekwang Yun; Shin-Hyun Jeong; Suhwan Kim 001 (ISLPED, 2019)

A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction. - Jaekwang Yun; Sangyoon Lee 006; Yong-Un Jeong; Shin-Hyun Jeong; Suhwan Kim 001 (A-SSCC, 2020)

A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces. - Hyunkyu Park 002; Jihwan Park; Jae-Whan Lee; Yong-Un Jeong; Shin-Hyun Jeong; Suhwan Kim 001; Joo-Hyung Chae (ISCAS, 2021)

A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface. - Sungphil Choi; Yong-Un Jeong; Joo-Hyung Chae; Shin-Hyun Jeong; Suhwan Kim 001 (IEEE Access, 2021)

A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface. - Yong-Un Jeong; Hyunkyu Park 002; Changho Hyun; Joo-Hyung Chae; Shin-Hyun Jeong; Suhwan Kim 001 (IEEE J. Solid State Circuits, 2021)

A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces. - Yong-Un Jeong; Sungphil Choi; Joo-Hyung Chae; Jaekwang Yun; Shin-Hyun Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

An N/PBTI-Isolated BTI Monitor With a Configurable Switching Network and Calibration for Process Variation in Memory Periphery. - Shin-Hyun Jeong; Yong-Un Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An Energy and Area-Efficient PAM-4 Data Coding Scheme with Embedded Supply Noise Stabilization for Single-Ended Memory Interface. - Giyeong Heo; Younghwan Chang; Yong-Un Jeong; Jaekwang Yun; Jusung Lee; Shin-Hyun Jeong; Sanghyuk Seo; Suhwan Kim 001 (CICC, 2025)