A 60-ns 16-Mb flash EEPROM with program and erase sequence controller. - Takeshi Nakayama; Shin'ichi Kobayashi; Yoshikazu Miyawaki; Yasushi Terada; Natsuo Ajika; Makoto Ohi; Hideaki Arima; Takayuki Matsukawa; Tsutomu Yoshihara; Kimio Suzuki (IEEE J. Solid State Circuits, 1991)

A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories. - Yoshikazu Miyawaki; Takeshi Nakayama; Shin'ichi Kobayashi; Natsuo Ajika; Makoto Ohi; Yasushi Terada; Hideaki Arima; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1992)

Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory. - Shin'ichi Kobayashi; Hiroaki Nakai; Yuichi Kunori; Takeshi Nakayama; Yoshikazu Miyawaki; Yasushi Terada; Hiroshi Onoda; Natsuo Ajika; Masahiro Hatanaka; Hirokazu Miyoshi; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1994)

A Functional Model of Cortico-Basal Ganglia Loop in Motor Control. - Shin'ichi Kobayashi; Koji Ito (ICONIP, 1998)

Technology Trends Analysis from the Internet Resources. - Shin'ichi Kobayashi; Yasuyuki Shirai; Kazuo Hiyane; Fumihiro Kumeno; Hiroshi Inujima; Noriyoshi Yamauchi (PAKDD, 2005)

A Methodology for Planning R&D Topics in IT Field. - Shin'ichi Kobayashi; Fumihiro Kumeno; Yasuyuki Shirai; Shin-ya Sano; Satoshi Nishiyama; Naoki Asai; Akio Sato; Hiroshi Inujima (HICSS, 2006)