An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD. - Tomonori Izumi; Shin'ichi Kouyama; Hiroyuki Ochi; Yukihiro Nakamura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices. - Kentaro Nakahara; Shin'ichi Kouyama; Tomonori Izumi; Hiroyuki Ochi; Yukihiro Nakamura (FPGA, 2006)

Fault Tolerant Reconfigurable Device Based on Autonomous-Repair Cells. - Kentaro Nakahara; Shin'ichi Kouyama; Tomonori Izumi; Hiroyuki Ochi; Yukihiro Nakamura (FPL, 2006)

Fault Tolerant Dynamic Reconfigurable Device Based on EDAC with Rollback. - Kentaro Nakahara; Shin'ichi Kouyama; Tomonori Izumi; Hiroyuki Ochi; Yukihiro Nakamura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture. - Shin'ichi Kouyama; Tomonori Izumi; Hiroyuki Ochi; Yukihiro Nakamura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device. - Kentaro Nakahara; Shin'ichi Kouyama; Tomonori Izumi; Hiroyuki Ochi; Yukihiro Nakamura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)