An 8-qubit quantum-circuit processor. - Shin-ichi O'Uchi; Minoru Fujishima; Koichiro Hoh (ISCAS (5), 2002)

CMOS Integrated DNA Chip for Quantitative DNA Analysis. - Nobuhiro Gemma; Shin-ichi O'Uchi; Hideyuki Funaki; Jun Okada; Sadato Hongo (ISSCC, 2006)

Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology. - Shin-ichi O'Uchi; Meishoku Masahara; Kunihiro Sakamoto; Kazuhiko Endo; Yongxun Liu; Takashi Matsukawa; Toshihiro Sekigawa; Hanpei Koike; Eiichi Suzuki (CICC, 2007)

FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction. - Shin-ichi O'Uchi; Meishoku Masahara; Kazuhiko Endo; Yongxun Liu; Takashi Matsukawa; Kunihiro Sakamoto; Toshihiro Sekigawa; Hanpei Koike; Eiichi Suzuki (IEICE Trans. Electron., 2008)

Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFET. - Shin-ichi O'Uchi; Kazuhiko Endo; Yongxun Liu; Tadashi Nakagawa; Takashi Matsukawa; Yuki Ishikawa; Junichi Tsukada; Toshihiro Sekigawa; Hanpei Koike; Kunihiro Sakamoto; Meishoku Masahara (CICC, 2010)

0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits. - Shin-ichi O'Uchi; Kazuhiko Endo; Yongxun Liu; Tadashi Nakagawa; Takashi Matsukawa; Yuki Ishikawa; Junichi Tsukada; Hiromi Yamauchi; Toshihiro Sekigawa; Hanpei Koike; Kunihiro Sakamoto; Meishoku Masahara (ESSCIRC, 2010)

A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology. - Shin-ichi O'Uchi; Kazuhiko Endo; Takashi Matsukawa; Yongxun Liu; Tadashi Nakagawa; Yuki Ishikawa; Junichi Tsukada; Hiromi Yamauchi; Toshihiro Sekigawa; Hanpei Koike; Kunihiro Sakamoto; Meishoku Masahara (IEICE Trans. Electron., 2012)

High-Frequency Precise Characterization of Intrinsic FinFET Channel. - Hideo Sakai; Shin-ichi O'Uchi; Takashi Matsukawa; Kazuhiko Endo; Yongxun Liu; Junichi Tsukada; Yuki Ishikawa; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike; Kunihiro Sakamoto; Meishoku Masahara; et al. (IEICE Trans. Electron., 2012)

Guidelines for symmetric threshold voltage in tunnel FinFETs with single and dual metal gate electrodes. - Wataru Mizubayashi; Koichi Fukuda; Takahiro Mori; Kazuhiko Endo; Yongxun Liu; Takashi Matsukawa; Shin-ichi O'Uchi; Yuki Ishikawa; Shinji Migita; Yukinori Morita; Akihito Tanabe; Junichi Tsukada; et al. (ESSDERC, 2013)

Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations. - Yukinori Morita; Takahiro Mori; Shinji Migita; Wataru Mizubayashi; Akihito Tanabe; Koichi Fukuda; Takashi Matsukawa; Kazuhiko Endo; Shin-ichi O'Uchi; Yongxun Liu; Meishoku Masahara; Hiroyuki Ota (ESSDERC, 2013)

Independent-Double-Gate FinFET SRAM Technology. - Kazuhiko Endo; Shin-ichi O'Uchi; Takashi Matsukawa; Yongxun Liu; Meishoku Masahara (IEICE Trans. Electron., 2013)

Variation behavior of tunnel-FETs originated from dopant concentration at source region and channel edge configuration. - Shinji Migita; Takashi Matsukawa; Takahiro Mori; Koichi Fukuda; Yukinori Morita; Wataru Mizubayashi; Kazuhiko Endo; Yongxun Liu; Shin-ichi O'Uchi; Meishoku Masahara; Hiroyuki Ota (ESSDERC, 2014)

Improvement of epitaxial channel quality on heavily arsenic- and boron-doped Si surfaces and impact on tunnel FET performance. - Yukinori Morita; Takahiro Mori; Shinji Migita; Wataru Mizubayashi; Koichi Fukuda; Takashi Matsukawa; Kazuhiko Endo; Shin-ichi O'Uchi; Yongxun Liu; Meishoku Masahara; Hiroyuki Ota (ESSDERC, 2014)

SOI CMOS Voltage Multiplier Circuits with Body Bias Control Technique for Battery-Less Wireless Sensor System. - Yasushi Igarashi; Tadashi Chiba; Shin-ichi O'Uchi; Meishoku Masahara; Kunihiro Sakamoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

PBTI for N-type tunnel FinFETs. - Wataru Mizubayashi; Takahiro Mori; Koichi Fukuda; Yongxun Liu; Takashi Matsukawa; Yuki Ishikawa; Kazuhiko Endo; Shin-ichi O'Uchi; Junichi Tsukada; Hiromi Yamauchi; Yukinori Morita; Shinji Migita; et al. (ICICDT, 2015)

Fully Integrated, 100-mV Minimum Input Voltage Converter With Gate-Boosted Charge Pump Kick-Started by LC Oscillator for Energy Harvesting. - Hiroshi Fuketa; Shin-ichi O'Uchi; Takashi Matsukawa (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 0.3-V 1-µW Super-Regenerative Ultrasound Wake-Up Receiver With Power Scalability. - Hiroshi Fuketa; Shin-ichi O'Uchi; Takashi Matsukawa (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Closed-Form Expression for Minimum Operating Voltage of CMOS D Flip-Flop. - Hiroshi Fuketa; Shin-ichi O'Uchi; Takashi Matsukawa (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Image-Classifier Deep Convolutional Neural Network Training by 9-bit Dedicated Hardware to Realize Validation Accuracy and Energy Efficiency Superior to the Half Precision Floating Point Format. - Shin-ichi O'Uchi; Hiroshi Fuketa; Tsutomu Ikegami; Wakana Nogami; Takashi Matsukawa; Tomohiro Kudoh; Ryousei Takano (ISCAS, 2018)

Optimizing Weight Value Quantization for CNN Inference. - Wakana Nogami; Tsutomu Ikegami; Shin-ichi O'Uchi; Ryousei Takano; Tomohiro Kudoh (IJCNN, 2019)

Perturbative GAN: GAN with Perturbation Layers. - Yuma Kishi; Tsutomu Ikegami; Shin-ichi O'Uchi; Ryousei Takano; Wakana Nogami; Tomohiro Kudoh (CoRR, 2019)

Short Floating-Point CNN Accelerator for Brain-Computer Interface to Decode Visual Information. - Shin-ichi O'Uchi; Ryusuke Hayashi (ISCAS, 2022)

Low-Precision Quantization Techniques for Hardware-Implementation-Friendly BERT Models. - Xinpei Zhang; Yi Ding; Mingfei Yu; Shin-ichi O'Uchi; Masahiro Fujita (ISQED, 2022)