Design of hardware algorithms by recurrence relations. - Shin'ichi Wakabayashi; Tohru Kikuno; Noriyoshi Yoshida (Syst. Comput. Jpn., 1985)

Visualized and modeless programming environment for form manipulation language. - Jun'ichi Miyao; Shin'ichi Wakabayashi; Noriyoshi Yoshida; Yasushi Ohtahara (VL, 1989)

An optimal channel pin assignment with multiple intervals for building block layout. - Tetsushi Koide; Shin'ichi Wakabayashi; Noriyoshi Yoshida (EURO-DAC, 1992)

A new global routing algorithm for over-the-cell routing in standard cell layouts. - Tetsushi Koide; Shin'ichi Wakabayashi; Noriyoshi Yoshida (EURO-DAC, 1993)

Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints. - Shin'ichi Wakabayashi; Hiroshi Kusumoto; Hideki Mishima; Tetsushi Koide; Noriyoshi Yoshida (ISCAS, 1993)

On Three-Way Graph Partitioning. - Yoko Kamidoi; Shin'ichi Wakabayashi; Noriyoshi Yoshida (ISCAS, 1994)

A Floorplanning Method with Topological Constraint Manipulation. - Tetsushi Koide; Yoshinori Katsura; Katsumi Yamatani; Shin'ichi Wakabayashi; Noriyoshi Yoshida (ISCAS, 1994)

A Systolic Graph Partitioning Algorithm for VLSI Design. - Shin'ichi Wakabayashi; Kazunori Isomoto; Tetsushi Koide; Noriyoshi Yoshida (ISCAS, 1994)

A new system partitioning method under performance and physical constraints for multi-chip modules. - Yoshinori Katsura; Tetsushi Koide; Shin'ichi Wakabayashi; Noriyoshi Yoshida (ASP-DAC, 1995)

A new performance driven placement method with the Elmore delay model for row based VLSIs. - Tetsushi Koide; Mitsuhiro Ono; Shin'ichi Wakabayashi; Yutaka Nishimaru (ASP-DAC, 1995)

A three-layer over-cell multi-channel routing method for a new cell model. - Masahiro Tsuchiya; Tetsushi Koide; Shin'ichi Wakabayashi; Noriyoshi Yoshida (ASP-DAC, 1995)

An MCM Routing Algorithm Considering Crosstalk. - Tetsuya Miyoshi; Shin'ichi Wakabayashi; Tetsushi Koide; Noriyoshi Yoshida (ISCAS, 1995)

A Verification Algorithm for Logic Circuits with Internal Variables. - Toshihiro Nakaoa; Shin'ichi Wakabayashi; Tetsushi Koide; Noriyoshi Yoshida (ISCAS, 1995)

A three-layer over-the-cell multi-channel router for a new cell model. - Tetsushi Koide; Masahiro Tsuchiya; Shin'ichi Wakabayashi; Noriyoshi Yoshida (Integr., 1996)

Pin assignment with global routing for VLSI building block layout. - Tetsushi Koide; Shin'ichi Wakabayashi; Noriyoshi Yoshida (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs. - Tetsushi Koide; Mitsuhiro Ono; Shin'ichi Wakabayashi; Yutaka Nishimaru (ASP-DAC, 1997)

A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs. - Tetsushi Koide; Shin'ichi Wakabayashi; Mitsuhiro Ono; Yutaka Nishimaru; Noriyoshi Yoshida (Integr., 1997)

A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. - Tetsushi Koide; Shin'ichi Wakabayashi (ASP-DAC, 1998)

Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm. - Koichi Hatta; Masashige Suzuki; Shin'ichi Wakabayashi; Tetsushi Koide (PPSN, 1998)

Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. - Koichi Hatta; Shin'ichi Wakabayashi; Tetsushi Koide (ASP-DAC, 1999)

An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. - Shin'ichi Wakabayashi; Tetsushi Koide; Naoyoshi Toshine; Mutsuaki Goto; Yoshikatsu Nakayama; Koichi Hatta (ASP-DAC, 1999)

A timing-driven floorplanning algorithm with the Elmore delay model for building block layout. - Tetsushi Koide; Shin'ichi Wakabayashi (Integr., 1999)

Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. - Takahiro Deguchi; Tetsushi Koide; Shin'ichi Wakabayashi (ASP-DAC, 2000)

Genetic algorithm accelerator GAA-II. - Shin'ichi Wakabayashi; Tetsushi Koide; Naoyoshi Toshine; Masataka Yamane; Hajime Ueno (ASP-DAC, 2000)

An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair. - Shingo Nakaya; Tetsushi Koide; Shin'ichi Wakabayashi (ISCAS, 2000)

Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual. - Koichi Hatta; Shin'ichi Wakabayashi; Tetsushi Koide (Syst. Comput. Jpn., 2001)

A hierarchical standard cell placement method based on a new cluster placement model. - Shin'ichi Wakabayashi; Nobuyuki Iwauchi; Hajime Kubota (APCCAS (1), 2002)

A Divide-and-Conquer Approach to the Minimum k-Way Cut Problem. - Yoko Kamidoi; Shin'ichi Wakabayashi; Noriyoshi Yoshida (Algorithmica, 2002)

A Performance-Driven Floorplanning Method with Interconnect Performance Estimation. - Shinya Yamasaki; Shingo Nakaya; Shin'ichi Wakabayashi; Tetsushi Koide (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time. - Shigeki Takekawa; Shin'ichi Wakabayashi; Tetsushi Koide (Syst. Comput. Jpn., 2002)

An Instance-Specific Hardware Algorithm for Finding a Maximum Clique. - Shin'ichi Wakabayashi; Kenji Kikuchi (FPL, 2004)

Solving the Minimum Dominating Set Problem with Instance-Specific Hardware on FPGAs. - Shin'ichi Wakabayashi; Kenji Kikuchi (FPT, 2005)

An Algorithm for Computing Global-Based Outlier Degrees on Data Sets. - Takeshi Fushimi; Yoko Kamidoi; Shin'ichi Wakabayashi (ICDE Workshops, 2005)

Feature Extraction of Clusters Based on FlexDice. - Tomotake Nakamura; Yoko Kamidoi; Shin'ichi Wakabayashi; Noriyoshi Yoshida (ICDE Workshops, 2005)

A Clustering Method Using an Irregular Size Cell Graph. - Tomotake Nakamura; Yoko Kamidoi; Shin'ichi Wakabayashi; Noriyoshi Yoshida (RIDE, 2005)

FPGA implementation of tabu search for the quadratic assignment problem. - Shin'ichi Wakabayashi; Yoshihiro Kimura; Shinobu Nagayama (FPT, 2006)

A Decision Method of Attribute Importance for Classification by Outlier Detection. - Tomotake Nakamura; Yoko Kamidoi; Shin'ichi Wakabayashi; Noriyoshi Yoshida (ICDE Workshops, 2006)

A Systolic Algorithm for the Quadratic Assignment Problem and its FPGA Implementation. - Yoshihiro Kimura; Shin'ichi Wakabayashi; Shinobu Nagayama (FPT, 2007)

A Parallel Multistage Metaheuristic Algorithm for VLSI Floorplanning. - Takayoshi Shimazu; Shin'ichi Wakabayashi; Shinobu Nagayama (PDPTA, 2007)

A systolic regular expression pattern matching engine and its application to network intrusion detection. - Yosuke Kawanaka; Shin'ichi Wakabayashi; Shinobu Nagayama (FPT, 2008)

A Systolic String Matching Algorithm for High-Speed Recognition of a Restricted Regular Set. - Yosuke Kawanaka; Shin'ichi Wakabayashi; Shinobu Nagayama (ERSA, 2009)

An FPGA-based text search engine for approximate regular expression matching. - Yuichiro Utan; Shin'ichi Wakabayashi; Shinobu Nagayama (FPT, 2010)

A Design Method for Programmable Two-Variable Discrete Function Generators Using Spline and Bilinear Interpolations. - Satoru Nakano; Yoichi Wakaba; Shinobu Nagayama; Shin'ichi Wakabayashi (DSD, 2011)

An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators. - Yoichi Wakaba; Masato Inagi; Shin'ichi Wakabayashi; Shinobu Nagayama (FPL, 2011)

A Multithreaded Parallel Global Routing Method with Overlapped Routing Regions. - Yasuhiro Shintani; Masato Inagi; Shinobu Nagayama; Shin'ichi Wakabayashi (DSD, 2013)

A Flexible and Compact Regular Expression Matching Engine Using Partial Reconfiguration for FPGA. - Yoichi Wakaba; Shinobu Nagayama; Shin'ichi Wakabayashi; Masato Inagi (DSD, 2013)

An ILP-Based Optimal Circuit Mapping Method for PLDs. - Hiroki Nishiyama 003; Masato Inagi; Shin'ichi Wakabayashi; Shinobu Nagayama; Keisuke Inoue; Mineo Kaneko (IPDPS Workshops, 2014)

An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating. - Yoichi Wakaba; Shin'ichi Wakabayashi; Shinobu Nagayama; Masato Inagi (IPSJ Trans. Syst. LSI Des. Methodol., 2014)

Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies. - Masato Inagi; Yuichi Nakamura 002; Yasuhiro Takashima; Shin'ichi Wakabayashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

An efficient FPGA implementation of Mahalanobis distance-based outlier detection for streaming data. - Yuto Arai; Shin'ichi Wakabayashi; Shinobu Nagayama; Masato Inagi (FPT, 2016)

An Approximate Nearest Neighbor Search Algorithm Using Distance-Based Hashing. - Yuri Itotani; Shin'ichi Wakabayashi; Shinobu Nagayama; Masato Inagi (DEXA (2), 2018)

Novel Feature Vectors Considering Distances between Wires for Lithography Hotspot Detection. - Gaku Kataoka; Masato Inagi; Shinobu Nagayama; Shin'ichi Wakabayashi (DSD, 2018)

A Nearest Neighbor Search Engine Using Distance-Based Hashing. - Toshitaka Ito; Yuri Itotani; Shin'ichi Wakabayashi; Shinobu Nagayama; Masato Inagi (FPT, 2018)

A Protocol for Preventing Transaction Commitment without Recipient's Authorization on Blockchain. - Ryosuke Yamauchi; Yoko Kamidoi; Shin'ichi Wakabayashi (COMPSAC (1), 2019)

A Framework for Fast MapReduce Processing Considering Sensitive Data on Hybrid Clouds. - Shun Kawamoto; Yoko Kamidoi; Shin'ichi Wakabayashi (COMPSAC, 2020)

A Verifiable Secret Sharing Scheme without Using Multi-Party Computations. - Takumi Makino; Yoko Kamidoi; Shin'ichi Wakabayashi (COMPSAC, 2020)

A Protocol for Preventing Transaction Commitment Without Recipient's Authorization on Blockchain and It's Implementation. - Yoko Kamidoi; Ryousuke Yamauchi; Shin'ichi Wakabayashi (IEEE Access, 2021)

Introduction of a New Method for Preventing Recipient Unapproved Transactions to Bitcoin Wallet. - Chuki Hayama; Yoko Kamidoi; Shin'ichi Wakabayashi (COMPSAC, 2022)

Feature Vectors Based on Wire Width and Distance for Lithography Hotspot Detection. - Gaku Kataoka; Masahiro Yamamoto; Masato Inagi; Shinobu Nagayama; Shin'ichi Wakabayashi (IPSJ Trans. Syst. LSI Des. Methodol., 2023)

Enhancing Security of Generalization Methods Based on m-Invariance for Dynamic Data Publication. - Fusu Zhang; Yoko Kamidoi; Shin'ichi Wakabayashi (COMPSAC, 2024)

A Proposal of Equivalence Classes in Maximally Asymmetric Functions and Their Application to Benchmark Generation. - Rie Kometani; Shinobu Nagayama; Martin Lukac; Masato Inagi; Shin'ichi Wakabayashi (ISMVL, 2024)