Limitations and challenges of multigigabit DRAM chip design. - Kiyoo Itoh 001; Yoshinobu Nakagome; Shin'ichiro Kimura; Takao Watanabe (IEEE J. Solid State Circuits, 1997)

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme. - Hitoshi Tanaka; Masakazu Aoki; Takeshi Sakata; Shin'ichiro Kimura; Narumi Sakashita; Hideto Hidaka; Tadashi Tachibana; Katsutaka Kimura (IEEE J. Solid State Circuits, 1999)

Reliability issues of silicon LSIs facing 100-nm technology node. - Eiji Takeda; Eiichi Murakami; Kazuyoshi Torii; Yutaka Okuyama; Eishi Ebe; Kenji Hinode; Shin'ichiro Kimura (Microelectron. Reliab., 2002)