1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS. - Shin'ichiro Mutoh; Takakuni Douseki; Yasuyuki Matsuya; Takahko Aoki; Satoshi Shigematsu; Junzo Yamada (IEEE J. Solid State Circuits, 1995)

A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application. - Shinichiro Mutoh; Satoshi Shigematsu; Yasuyuki Matsuya; H. Fukuda; T. Kaneko; Junzo Yamada (IEEE J. Solid State Circuits, 1996)

A 1-V high-speed MTCMOS circuit scheme for power-down application circuits. - Satoshi Shigematsu; Shin'ichiro Mutoh; Yasuyuki Matsuya; Yasuyuki Tanabe; Junzo Yamada (IEEE J. Solid State Circuits, 1997)

Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs. - Shinichiro Mutoh; Satoshi Shigematsu; Yoshinori Gotoh; Shinsuke Konaka (ASP-DAC, 1999)

A Mirror Metaphor Interaction System: Touching Remote Real Objects in an Augmented Reality Environment. - Eiichi Hosoya; Miki Kitabata; Hidenori Sato; Ikuo Harada; Hisao Nojima; Fumiharu Morisawa; Shinichiro Mutoh; Akira Onozawa (ISMAR, 2003)

A 2-Mb/s, UHF-band, wireless sensor node for real-time multi-point sensing. - Koji Fujii; Jun Terada; Junichi Kodate; Tsuneo Tsukahara; Shin'ichiro Mutoh; Yuichi Kado (ISCAS (4), 2004)

A 1-V Cyclic A/D Converter Using FD-SOI Sample/Hold Circuits for Sensor Networks. - Jun Terada; Yasuyuki Matsuya; Shin'ichiro Mutoh; Yuichi Kado (IEICE Trans. Electron., 2005)

Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit. - Shunji Nakata; Hirotsugu Suzuki; Ryota Honda; Takahito Kusumoto; Shin'ichiro Mutoh; Hiroshi Makino; Masayuki Miyama; Yoshio Matsuda (ISCAS, 2010)

Nano-watt power management and vibration sensing on a dust-size batteryless sensor node for ambient intelligence applications. - Toshishige Shimamura; Mamoru Ugajin; Kenji Suzuki; Kazuyoshi Ono; Norio Sato; Kei Kuwabara; Hiroki Morimura; Shin'ichiro Mutoh (ISSCC, 2010)

Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation. - Shunji Nakata; Shin'ichiro Mutoh; Hiroshi Makino; Masayuki Miyama; Yoshio Matsuda (IEICE Electron. Express, 2010)

Design and Performance of a Sub-Nano-Ampere Two-Stage Power Management Circuit in 0.35-µm CMOS for Dust-Size Sensor Nodes. - Mamoru Ugajin; Toshishige Shimamura; Shin'ichiro Mutoh; Mitsuru Harada (IEICE Trans. Electron., 2011)

Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. - Hiroshi Makino; Shunji Nakata; Hirotsugu Suzuki; Shin'ichiro Mutoh; Masayuki Miyama; Tsutomu Yoshimura; Shuhei Iwade; Yoshio Matsuda (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield. - Hiroshi Makino; Shunji Nakata; Hirotsugu Suzuki; Shin'ichiro Mutoh; Masayuki Miyama; Tsutomu Yoshimura; Shuhei Iwade; Yoshio Matsuda (IET Circuits Devices Syst., 2012)

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology. - Shunji Nakata; Ryota Honda; Hiroshi Makino; Shin'ichiro Mutoh; Masayuki Miyama; Yoshio Matsuda (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Session 11 overview: Emerging memory and wireless technology. - Fu-Lung Hsueh; Shinichiro Mutoh (ISSCC, 2013)

Session 24 overview: Secure, efficient circuits for IoT: Technology directions subcommittee. - Chris Nicol; Shinichiro Mutoh (ISSCC, 2015)