Knowledge-Based Approach for Adaptive Recognition of Drawings. - Shin'ichiro Okazaki; Yoshitake Tsuji (Pattern Recognition, 1988)

A Real-Time Vision System Using Integrated Memory Array Processor Prototype LSI. - Yoshihiro Fujita; Nobuyuki Yamashita; Shin'ichiro Okazaki (MVA, 1992)

Imap: Integrated Memory Array Processor. - Yoshihiro Fujita; Nobuyuki Yamashita; Shin'ichiro Okazaki (J. Circuits Syst. Comput., 1992)

Dataflow Graph Optimization for Dataflow Architectures - A Dataflow Optimizing Compiler. - Sholin Kyo; Shin'ichiro Okazaki; Masanori Mizoguchi (ICPP (2), 1993)

A Compact 30GIPS Real-Time Vision System RVS-2. - Shin'ichiro Okazaki; Yoshihiro Fujita; Nobuyuki Yamashita (MVA, 1994)

A real-time vision system using an integrated memory array processor prototype. - Yoshihiro Fujita; Nobuyuki Yamashita; Shin'ichiro Okazaki (Mach. Vis. Appl., 1994)

A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM. - Nobuyuki Yamashita; Tohru Kimura; Yoshihiro Fujita; Yoshiharu Aimoto; Takashi Manabe; Shin'ichiro Okazaki; Kazuyuki Nakamura; Masakazu Yamashina (IEEE J. Solid State Circuits, 1994)

A compact real-time vision system using integrated memory array processor architecture. - Shin'ichiro Okazaki; Yoshihiro Fujita; Nobuyuki Yamashita (IEEE Trans. Circuits Syst. Video Technol., 1995)

Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications. - Tohru Kimura; Kazuyuki Nakamura; Yoshiharu Aimoto; Takashi Manabe; Nobuyuki Yamashita; Yoshihiro Fujita; Shin'ichiro Okazaki; Masakazu Yamashina (IEEE J. Solid State Circuits, 1995)

An integrated memory array processor with a synchronous-DRAM interface for real-time vision applications. - Nobuyuki Yamashita; Yoshihiro Fujita; Shin'ichiro Okazaki (ICPR, 1996)

IMAP-VISION: An SIMD Processor with High-Speed On-chip Memory and Large Capacity External Memory. - Yoshihiro Fujita; Nobuyuki Yamashita; Shin'ichiro Okazaki (MVA, 1996)

A 3.84 gips integrated memory array processor. - Yoshihiro Fujita; Nobuyuki Yamashita; Tohru Kimura; Kazuyuki Nakamura; Shin'ichiro Okazaki (Syst. Comput. Jpn., 1996)

IMAP-CE: a 51.2 GOPS video rate image processor with 128 VLIW processing elements. - Shorin Kyo; Takuya Koga; Shin'ichiro Okazaki (ICIP (3), 2001)

A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements. - Shorin Kyo; Takuya Koga; Shin'ichiro Okazaki; Ichiro Kuroda (IEEE J. Solid State Circuits, 2003)

A 51.2 GOPS Programmable Video Recognition Processor for Vision-Based Intelligent Cruise Control Applications. - Shorin Kyo; Takuya Koga; Shin'ichiro Okazaki; Ichiro Kuroda (IEICE Trans. Inf. Syst., 2004)

An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems. - Shorin Kyo; Shin'ichiro Okazaki; Tamio Arai (ISCA, 2005)

A low-cost mixed-mode parallel processor architecture for embedded systems. - Shorin Kyo; Takuya Koga; Hanno Lieske; Shouhei Nomoto; Shin'ichiro Okazaki (ICS, 2007)

An Integrated Memory Array Processor for Embedded Image Recognition Systems. - Shorin Kyo; Shin'ichiro Okazaki; Tamio Arai (IEEE Trans. Computers, 2007)

In-vehicle vision processors for driver assistance systems. - Shorin Kyo; Shin'ichiro Okazaki (ASP-DAC, 2008)

Overtaking Vehicle Detection Method and Its Implementation Using IMAPCAR Highly Parallel Image Processor. - Kazuyuki Sakurai; Shorin Kyo; Shin'ichiro Okazaki (IEICE Trans. Inf. Syst., 2008)

IMAPCAR2: A dynamic SIMD/MIMD mode switching processor for embedded systems. - Shorin Kyo; Shouhei Nomoto; Takuya Koga; Hanno Lieske; Shin'ichiro Okazaki (Hot Chips Symposium, 2009)

Mapping schemes of image recognition tasks onto highly parallel SIMD/MIMD processors. - Shorin Kyo; Shouhei Nomoto; Shin'ichiro Okazaki (ICDSC, 2009)

Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application. - Shouhei Nomoto; Shorin Kyo; Shin'ichiro Okazaki (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

A dynamic SIMD/MIMD mode switching processor for embedded real-time image recognition systems. - Shouhei Nomoto; Shorin Kyo; Shin'ichiro Okazaki (A-SSCC, 2011)

IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements. - Shorin Kyo; Shin'ichiro Okazaki (J. Signal Process. Syst., 2011)

Efficient data transfer operations for a SIMD processor array system. - Hanno Lieske; Shorin Kyo; Shouhei Nomoto; Sunao Torii; Yuki Kobayashi; Yasuyuki Ninomiya; Shin'ichiro Okazaki (ICASSP, 2012)